SCPA074 September   2024 TPLD1202

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Configuring the Pattern Generator in TPLD Using InterConnect Studio (ICS)
  5. 2Utilizing the Reset Input of the Pattern Generator
  6. 3Generating a Pattern Less Than 16 bits
  7. 4References

Generating a Pattern Less Than 16 bits

While the Pattern to Generate field will accept any value from 0x0000 to 0xFFFF, only the number of bits specified in the Size field will be used for the PGEN output. Figure 3-1 shows an example of a PGEN macro-cell configured with the Pattern to Generate 0xD1F2, but with a Size of 10, resulting in the lower 10 bits being used and the output pattern of 0x1F2.
 PGEN With Reset (10-bit Pattern, 0x1F2) Example Configuration in ICSFigure 3-1 PGEN With Reset (10-bit Pattern, 0x1F2) Example Configuration in ICS
 Logic Analyzer Capture of PGEN With Reset (10-bit Pattern, 0x1F2)Figure 3-2 Logic Analyzer Capture of PGEN With Reset (10-bit Pattern, 0x1F2)
 Logic Analyzer Capture of PGEN With Reset (10-bit Pattern, 0x1F2, Zoomed)Figure 3-3 Logic Analyzer Capture of PGEN With Reset (10-bit Pattern, 0x1F2, Zoomed)