SFFS011 February   2023 TPS560430-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Failure Mode Distribution (FMD)
  4. 3Functional Safety Failure In Time (FIT) Rates
  5. 4Pin Failure Mode Analysis (Pin FMA)

Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS560430-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to VIN (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • Device used within the 'Recommended Operating Conditions' and the 'Absolute Maximum Ratings' found in the appropriate device data sheet.
  • Configuration as shown in the 'Example Application Circuit' found in the appropriate device data sheet.

Figure 4-1 shows the TPS560430-Q1 pin diagram for the SOT-23-6 package. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the appropriate device data sheet.

GUID-4215E15F-370B-4D0F-BC5F-01D8D8D79D09-low.gifFigure 4-1 Pin Diagram
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
CB1No output voltageB
GND2Normal OperationD
FB3The regulator will operate at maximum duty cycle. Output voltage will rise to nearly the input voltage (VIN) level. Possible damage to customer load and/or output stage components may occur. No effect on device.B
EN4Loss of ENABLE functionality Device will remain in shutdown mode.B
VIN5Device will not operate. No output voltage will be generated. Output capacitors will discharge through input short. Large reverse current may damage device.A
SW6Damage to internal FET.A
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
CB1No output voltageB
GND2VOUT can be abnormal due to switching noise on analog circuits.B
FB3VOUT will be higher than programmed output voltage.B
EN4Loss of ENABLE functionality. Erratic operation; probable loss of regulation.B
VIN5No output voltageB
SW6No output voltageB
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
CB1GNDNo output voltageB
GND2FBThe regulator will operate at maximum duty cycle. Output voltage will rise to nearly the input voltage (VIN) level. Possible damage to customer load and/or output stage components can occur. No effect on device.B
FB3GNDThe regulator will operate at maximum duty cycle. Output voltage will rise to nearly the input voltage (VIN) level. Possible damage to customer load and/or output stage components can occur. No effect on device.B
EN4VINNo damage to device. Loss of ENABLE functionality.B
VIN5SWDamage to internal FETA
SW6VINDamage to internal FETA
Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
CB1No output voltage. CBOOT ESD clamp will run current to destruction.A
GND2No output voltage. Damage to other pins referred to GND.A
FB3If VIN exceeds 16 V, damage will occur. No output voltage.A
EN4No damage to device. Loss of ENABLE functionality.B
VIN5No effectD
SW6internal FETA