SFFS155 June 2021 TLV840-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLV840-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

CLASS	FAILURE EFFECTS
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Figure 4-1 shows the TLV840-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TLV840-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

VDD = 5 V, RESET pulled-up to VDD unless stated otherwise, and CT and MR pins are left floating

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

PIN NAME	PIN NO.	DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)	FAILURE EFFECT CLASS
RESET (open drain)	1	No damage to device, can affect functionality. Forces RESET to be asserted. Increased leakage current.	B
RESET (push-pull)	1	Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current.	A
VDD	2	No damage to device, can affect functionality. Shorts voltage supply to ground, increases current.	C
GND	3	Normal operation.	D
MR	4	Defined operation, no damage to device. Forces RESET to be asserted.	C
CT	5	No damage to device, can affect functionality. Forces RESET to be asserted.	B

Table 4-3 Pin FMA for Device Pins Open-Circuited

PIN NAME	PIN NO.	DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)	FAILURE EFFECT CLASS
RESET (open drain)	1	Reset functionality will be lost	B
RESET (push-pull)	1	Reset functionality will be lost	B
VDD	2	No damage to device, can affect functionality. Device is unpowered.	B
GND	3	No damage to device, can affect functionality. Device is unpowered.	C
MR	4	Normal operation.	D
CT	5	Normal operation.	D

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

PIN NAME	PIN NO.	SHORTED TO	DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)	FAILURE EFFECT CLASS
RESET (open drain)	1	VDD	Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current.	A
RESET (push-pull)	1	VDD	Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current.	A
VDD	2	GND	No damage to device, can affect functionality. Shorts voltage supply to ground, increases current.	C
GND	3	MR	Defined operation, no damage to device. Forces RESET to be asserted.	C
MR	4	CT	Normal operation	D
CT	5	RESET (open drain)	No damage to device, can affect performance. RESET does not pull high	C
CT	5	RESET (push-pull)	No damage to device, can affect performance. RESET does not pull high	C

Table 4-5 Pin FMA for Device Pins Short-Circuited to VDD supply

PIN NAME	PIN NO.	DESCRIPTION OF POTENTIAL FAILURE EFFECT(S)	FAILURE EFFECT CLASS
RESET (open - drain)	1	Might damage the device, can affect functionality. Forces RESET to be asserted. Increased leakage current.	A
RESET (push - pull)	1	Might damage the device, affects functionality. Increased leakage current.	A
VDD	2	Normal operation.	D
GND	3	No damage to device, can affect functionality. Shorts voltage supply to ground, increases current.	C
MR	4	Normal operation	D
MR (connected to GPIO or switch)	4	Affects functionality. Pin can't be shorted to GND or pulled low to assert RESET	B
CT	5	No effect however, can affect functionality if in use. No delay in RESET.	D
CT (connected to a capacitor)	5	Lost of RESET functionality.	B