SFFS208 August 2021 TLV6700-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TLV6700-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Figure 4-1 shows the TLV6700-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TLV6700-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section

Each pin is assesed individually
All other pins are configured correctly for device functionality
DSE Package pinout used for Pin Name and No.

Assumption yetc.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
OUTB	1	No change if GND pin is GND node	B
VDD	2	Main supply shorted out (no power to device)	B
INB-	3	OUTB goes high	B
INA+	4	OUTA goes low	B
GND	5	No change if same node as GND	D
OUTA	6	No change if GND pin is GND node	B

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
OUTB	1	OUTB cannot drive application load	B
VDD	2	Main suppy open (no power to device)	B
INB-	3	OUTB may be low or high	B
INA+	4	OUTA may be low or high	B
GND	5	Lowest voltage pin will drive GND pin internally (via diode)	A
OUTA	6	OUTA cannot drive application load	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effect(s)	Failure Effect Class
OUTB to VDD	1	2	Thermal stress due to high power dissipation	A
VDD to INB-	2	3	Output goes low	B
INB- to INA+	3	4	Output may be high or low	B
INA+ to GND	4	5	Outout goes low	B
GND to OUTA	5	6	No change if GND pin is GND node	B
OUTA to OUTB	6	1	Outoput goes low unless INA+ is above the reference and INB- is below the reference	B

Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
OUTB	1	Thermal stress due to high power dissipation	A
VDD	2	No change if same node as VDD	D
INB-	3	Outout goes low	B
INA+	4	Output goes high	B
GND	5	Main supply shorted out (no power to device)	B
OUTA	6	Thermal stress due to high power dissipation	A