SFFS278 October 2021 TLV7032-Q1 , TLV7042-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the TLV7032-Q1 and TLV7042-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to VEE (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to an adjacent pin (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TLV7032-Q1 and TLV7042-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TLV7032-Q1 and TLV7042-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section
Each pin is assesed individually
All other pins are configured correctly for device functionality
DGK Package pinout used for Pin Name and No.
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUTA | 1 | OUTA will be pulled low (Open-Drain) Thermal stress due to higher power dissipation (Push-Pull) | B A |
INA- | 2 | OUTA goes high if INA+ is more positive | B |
INA+ | 3 | OUTA goes low if INA- is more positive | B |
VEE | 4 | No change (same node) | D |
INB+ | 5 | OUTB goes low if INB- is more positive | B |
INB- | 6 | OUTB goes high if INB+ is more positive | B |
| OUTB | 7 | OUTB will be pulled low (Open-Drain) Thermal stress due to higher power dissipation (Push-Pull) | B A |
VCC | 8 | Main supply shorted out (no power to device) | B |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUTA | 1 | OUTA cannot drive application load (Open-Drain) OUTA cannot drive application load or toggle high (Push-Pull) | B |
INA- | 2 | OUTA may be high or low | B |
INA+ | 3 | OUTA may be low or high | B |
VEE | 4 | Lowest voltage pin will drive GND pin internally (via diode) | B |
INB+ | 5 | OUTB may be high or low | B |
INB- | 6 | OUTB may be high or low | B |
OUTB | 7 | OUTB cannot drive application load (Open-Drain) OUTB cannot drive application load or toggle high (Push-Pull) | B |
VCC | 8 | Main supply open (no power to device) | B |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUTA | 1 | Thermal stress due to high power dissipation | A |
INA- | 2 | OUTA goes low if INA+ is less positive | B |
INA+ | 3 | OUTA goes high if INA- is less positive | B |
VEE | 4 | Main supply shorted out (no power to device) | B |
| INB+ | 5 | OUTB goes high if INB- is less positive | B |
INB- | 6 | OUTB goes low if INB+ is less positive | B |
OUTB | 7 | Thermal stress due to high power dissipation | A |
VCC | 8 | No change (same node) | D |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
OUTA to INA- | 1 | 2 | OUTA may be high or low | B |
INA- to INA+ | 2 | 3 | OUTA may be high or low | B |
INA+ to VEE | 3 | 4 | OUTA goes low, if INA- is more positive | B |
VEE to INB+ | 4 | 5 | OUTB goes low, if INB- is more positive | B |
INB+ to INB- | 5 | 6 | OUTB may be high or low | B |
INB- to OUTB | 6 | 7 | OUTB may be high or low | B |
OUTB to VCC | 7 | 8 | Thermal stress due to higher power dissipation | A |
VCC to OUTA | 8 | 1 | Thermal stress due to higher power dissipation | A |