SFFS339 December   2022 TLIN1431-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Hardware Component Failure Modes Effects and Diagnostics Analysis (FMEDA)
    1. 2.1 Random Fault Estimation
      1. 2.1.1 Fault Rate Estimation Theory for Packaging
      2. 2.1.2 Fault Estimation Theory for Silicon Permanent Faults
      3. 2.1.3 Fault Estimation Theory for Silicon Transient Faults
      4. 2.1.4 The Classification of Failure Categories and Calculation
  4. 3Using the FMEDA Spreadsheet Tool
    1. 3.1 Mission Profile Tailoring Tab
      1. 3.1.1 Geographical Location
      2. 3.1.2 Life Cycle
      3. 3.1.3 Use Case Thermal Management Control (Theta-Ja) and Use Case Power
      4. 3.1.4 Safe vs Non-Safe (Safe Fail Fraction) for Each Component Type
      5. 3.1.5 Analog FIT Distribution Method
      6. 3.1.6 Operational Profile
    2. 3.2 Pin Level Tailoring Tab
    3. 3.3 Function and Diag Tailoring Tab
    4. 3.4 Diagnostic Coverage Tab
    5. 3.5 Customer Defined Diagnostics Tab
    6. 3.6 Totals - ISO26262 Tab
    7. 3.7 Details - ISO26262 Tab
    8. 3.8 Example Calculation of Metrics
      1. 3.8.1 Assumptions of Use for Calculation of Safety Metrics
      2. 3.8.2 Summary of ISO 26262 Safety Metrics at Device Level

2.1.2 Fault Estimation Theory for Silicon Permanent Faults

TI uses the IEC/TR 62380 model to estimate FIT rate due to silicon permanent faults. The IEC/TR 62380 model focuses primarily on gate oxide integrity type faults that are accelerated by voltage and temperature. This is a traditional approach to semiconductor fault modeling, as gate oxide failure is a primary wear-out mechanism. However, in recent product generations additional failure modes have become significant and are not always accelerated by the same conditions as a gate oxide failure. JEDEC JEP122G, "Failure Mechanisms and Models for Semiconductor Devices", can provide additional details. Management of these failure modes may require additional testing and diagnostics, which are not well comprehended in IEC 61508:2010 and ISO 26262:2011.

TI's application of the IEC/TR 62380 model follows the guidance found in ISO 26262-11:2018. Permanent faults are separated into five classes, each estimated with a separate intrinsic FIT rate: MOS digital circuits, low-power consumption SRAM, ROM, block erasable flash, and low voltage linear (analog). The process FIT factor of the five circuitry types is averaged, as the standard does not comprehend a process that allows integration of digital, analog, ROM, SRAM, and flash. Please note that some devices may not have every category listed above, in that case, the absent categories are excluded from the calculation. The automotive motor control profile is used as default in TI's estimates.