SFFS364 May   2022 TPS4811-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for TPS4811x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)

Gate output stuck high

13%

Gate output stuck low

40%

Gate output functional, not in specification voltage or timing

33%

Short circuit protection fails to trip or false trip

2%

IMON not in specification - current or timing

5%

UVLO, OV, TSD fails to trip or false trip

2%

Pin to Pin short any two pins

5%