SFFS364 May 2022 TPS4811-Q1
This section provides a Failure Mode Analysis (FMA) for the pins of the TPS4811x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-2 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TPS4811x-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS4811x-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
EN/UVLO | 1 | Normal operation. The device is disabled. | B |
| OV | 2 | TPS48110-Q1 Only. OV functionality is disabled. | B |
INP_G | 2 | TPS48111-Q1 Only. Normal operation. The G output is low and the external precharge FET is off. | B |
INP | 3 | Normal operation. The PD output is low and the external FET is off. | B |
FLT_T | 4 | Overtemperature fault diagnostic cannot be reported. | B |
FLT_I | 5 | Overcurrent fault diagnostic cannot be reported. | B |
GND | 6 | Normal operation | D |
IMON | 7 | IMON output cannot be reported. | B |
IWRN | 8 | Overcurrent does not get detected, hence overcurrent protection gets disabled. | B |
TMR | 9 | Overcurrent does not get detected, hence overcurrent protection gets disabled. | B |
DIODE | 10 | Overtemperature does not get detected, hence overtemperature protection gets disabled. | B |
N.C | 11 | TPS48110-Q1 Only. No effect. | D |
G | 11 | TPS48111-Q1 only. With G grounded, if the pin voltage between SRC and G exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on ESD circuit. | A |
BST | 12 | Gate Driver supply does not come up. FETs remain OFF. | B |
| SRC | 13 | Short-to-GND protection kicks in | B |
PD | 14 | With PD grounded, if the pin voltage between SRC and PD exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on ESD circuit. | A |
PU | 15 | Gate Driver supply gets short circuited. FETs remain OFF. | B |
CS- | 17 | Short circuit of input supply | B |
CS+ | 18 | With CS+ grounded, if the pin voltage between CS+ and CS– exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on ESD circuit. | A |
ISCP | 19 | With ISCP grounded, if the pin voltage between ISCP and CS– exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on ESD circuit. | A |
VS | 20 | Device supply grounded. Device does not power up. | B |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
EN/UVLO | 1 | Internal pulldown brings EN/UVLO to low, disabling the device. | B |
| OV | 2 | TPS48110-Q1 only. OV functionality gets disabled as OV gets internally pulled down to 0 V. | B |
INP_G | 2 | TPS48111-Q1 only. Internal pulldown brings INP_G to low, pulling G output low. | B |
INP | 3 | Internal pulldown brings INP to low, pulling PD output low. | B |
FLT_T | 4 | Overtemperature fault diagnostic cannot be reported. | B |
FLT_I | 5 | Overcurrent fault diagnostic cannot be reported. | B |
GND | 6 | Device does not power up and is disabled. | B |
IMON | 7 | IMON voltage can get clamped to internal supply of 6.5 V. | B |
IWRN | 8 | IWRN voltage can get clamped to internal supply of 4.5 V. | B |
TMR | 9 | Overcurrent response time and auto-retry duration gets reduced to device minimum setting. | C |
DIODE | 10 | Overtemperature protection gets disabled. | B |
N.C | 11 | No effect | D |
G | 11 | G output does not get controlled. | B |
BST | 12 | External FET may get turned ON and OFF repetitively due to no capacitor connection at BST pin. | B |
| SRC | 13 | The external FET does turn OFF as the FET's source got disconnected from the internal pulldown driver. | B |
PD | 14 | The external FET does not turn OFF as the FET's GATE disconnected from the internal pulldown driver. | B |
PU | 15 | The external FET does not turn ON as the FET's GATE disconnected from the internal pullup driver. | B |
CS- | 17 | CS– gets internally clamped to CS+ minus two diode drops. If IWRN feature is used, then the external FET may not turn ON due to false overcurrent detection. | B |
CS+ | 18 | IMON and overcurrent protection features get disabled. | B |
ISCP | 19 | Short-circuit protection feature gets disabled. | B |
VS | 20 | Device does not get powered up and is disabled. | B |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
EN/UVLO | 1 | 2 (OV) | TPS48110-Q1 only. When EN/UVLO is driven high then based on the EN/UVLO level the device may detect the OV event and turn off the external FET. | B |
| EN/UVLO | 1 | 2 (INP_G) | TPS48111-Q1 only. When EN/UVLO is driven high then based on the EN/UVLO level INP_G may get detected high and G may go high turning ON the external precharge FET. | B |
| OV | 2 | 3 (INP) | TPS48110-Q1 only. When INP is driven high then based on INP level the device may detect the OV event and turn off the external FET. | B |
INP_G | 2 | 3 (INP) | TPS48111-Q1 only. Both PU/PD and G are controlled together. | B |
INP | 3 | 4 (FLT_T) | When an overtemperature fault occurs, then INP gets pulled low and stays latched off in this state. | B |
FLT_T | 4 | 5 (FLT_I) | FLT_T and FLT_I gets ORd together. | B |
FLT_I | 5 | 6 (GND) | Overcurrent fault does not get indicated. | B |
GND | 6 | 7 (IMON) | IMON output does not get reported. | B |
IMON | 7 | 8 (IWRN) | IMON output range and IWRN set point gets changed based on the total bias currents flowing through the IMON and IWRN resistors. | C |
IWRN | 8 | 9 (TMR) | TMR and IWRN thresholds get affected. External FET shuts off at a different threshold than set by IWRN. During an overcurrent fault, TMR feature become inactive and the device is in latch-off mode. | C |
TMR | 9 | 10 (DIODE) | Auto-retry feature is disabled. Overtemperature feature may give false errors and cause the external FET to turn OFF. | B |
N.C | 11 | 12 (BST) | TPS48110-Q1 only. No effect. | D |
G | 11 | 12 (BST) | TPS48111-Q1 only. When INP_G is driven low, BST (Gate driver supply) gets loaded through the internal G pulldown switch. Gate driver UVLO hits resulting in turning off the external FETs. | B |
BST | 12 | 13 (SRC) | Gate drive supply gets shorted and external FETs do not turn ON. | B |
| SRC | 13 | 14 (PD) | Shorting of the pulldown switch (between PD and SRC) of the internal gate driver. External FET remains OFF. | B |
PD | 14 | 15 (PU) | Turn ON and OFF speeds of the external FETs may get impacted. | C |
CS- | 17 | 18 (CS+) | Bypasses the external current sense resistor. IMON, OCP features get disabled. | B |
CS+ | 18 | 19 (ISCP) | Short-circuit threshold gets reduced. | C |
ISCP | 19 | 20 (VS) | Short-circuit protection gets set to minimum setting. | C |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
EN/UVLO | 1 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
| OV | 2 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
INP_G | 2 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
INP | 3 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
FLT_T | 4 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
FLT_I | 5 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
GND | 6 | Supply power is bypassed and device doe not turn on. | B |
IMON | 7 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
IWRN | 8 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
TMR | 9 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
DIODE | 10 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
N.C | 11 | TPS48110-Q1 only. No effect. | D |
G | 11 | TPS48111-Q1 only. If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
BST | 12 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
| SRC | 13 | Output stuck on to supply | B |
PD | 14 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
PU | 15 | If pin voltage exceeds the pin data sheet range, it may cause device damage due to voltage breakdown on the ESD circuit. | A |
CS- | 17 | In the application, the external sense resistor gets bypassed and IMON, overcurrent and short-circuit protection do not work. | A |
CS+ | 18 | IMON and IWRN outputs get saturated. External FET may get turned OFF. | B |
ISCP | 19 | Short-circuit protection gets set to minimum setting. | C |
VS | 20 | No effect | D |