SFFS661 November 2023 LMR38015-Q1 , LMR38025-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the LMR38015-Q1, LMR38025-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the LMR38015-Q1, LMR38025-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LMR38015-Q1, LMR38025-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Application circuit, as per the LMR38015-Q1, LMR38025-Q1 datasheet
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| GND | 1/2 | Normal operation | D |
| EN | 3 | VOUT = 0 V | B |
| VIN | 5/6 | VOUT = 0 V | B |
| RT/SYNC | 7 | Switching Frequency >> 3 MHz | C |
| FB | 8 | VOUT >> than programmed output voltage | B |
| PG | 9 | No power good function | B |
| BOOT | 10 | VOUT = 0 V | B |
| SW | 11/12 | Damage to HS FET | A |
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| GND | 1/2 | VOUT might be abnormal due to switching noise on analog circuits | B |
| EN | 3 | Device can shut off | B |
| VIN | 5/6 | Device can shut off | B |
| RT/SYNC | 7 | No Switching frequency | B |
| FB | 8 | VOUT >> than programmed output voltage | B |
| PG | 9 | No power good function | B |
| BST | 10 | VOUT = 0 V | B |
| SW | 11/12 | VOUT = 0 V | B |
| Pin Name 1 | Pin Name 2 | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| GND | EN | VOUT = 0 V | B |
| EN | VIN | Normal Vout operation | B |
| FB | PG | VOUT less than programmed output voltage | B |
| PG | BOOT | PGOOD Pin ESD damage if BOOT pin voltage >20 V | A |
| BOOT | SW | VOUT = 0 V | B |
| Pin Name | Pin No | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| GND | 1/2 | VOUT = 0 V. Damage to other pins referred to GND. | A |
| EN | 3 | Device enabled | D |
| VIN | 5/6 | Normal mode | D |
| RT/SYNC | 7 | RT/SYNC Pin ESD damage if VIN > 5.5 V | A |
| FB | 8 | If VIN exceeds 5.5 V damage will occur. VOUT = 0 V | A |
| PG | 9 | PGOOD Pin ESD damage if VIN >20V | B |
| BOOT | 10 | VOUT = 0 V. CBOOT ESD clamp will run current to destruction | A |
| SW | 11/12 | Damage to LS FET | A |