SFFS819 May   2024 RES11A-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1  SOT-23-THIN Package: RES11A10-Q1
    2. 2.2  SOT-23-THIN Package: RES11A15-Q1
    3. 2.3  SOT-23-THIN Package: RES11A16-Q1
    4. 2.4  SOT-23-THIN Package: RES11A20-Q1
    5. 2.5  SOT-23-THIN Package: RES11A25-Q1
    6. 2.6  SOT-23-THIN Package: RES11A30-Q1
    7. 2.7  SOT-23-THIN Package: RES11A40-Q1
    8. 2.8  SOT-23-THIN Package: RES11A50-Q1
    9. 2.9  SOT-23-THIN Package: RES11A90-Q1
    10. 2.10 SOT-23-THIN Package: RES11A00-Q1
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)

2 Functional Safety Failure In Time (FIT) Rates

The RES11A-Q1 is a pair of resistor dividers implemented in a semiconductor process. The device has no active elements such as transistors or ESD cells, which complicates the calculation of effective FIT rates. As the tools conventionally used for this task are unable to parse a chip that contains zero active elements, the limit as the active element count goes to zero is used for all calculations reported in this document.

The Recommended Operating Conditions section of the RES11A-Q1 data sheet specifies a maximum sustained current through each RIN and RG resistor for long-term operation. For a given RES11A-Q1 device, the lesser of these two values defines the maximum sustained divider current. The maximum divider impedance occurs in the event that the absolute tolerance of each resistor is +12% from the nominal value, and results in the highest possible values for RG and RIN. The square of the maximum sustained divider current, multiplied by the maximum divider impedance, thus defines the maximum power dissipation of the divider. As the RES11A-Q1 contains two dividers per package, multiplying this result by two gives the maximum recommended power dissipation of the device.

The maximum allowed power dissipation does also depend on environmental conditions. In cases where the ambient temperature combined with the self-heating associated with a given power dissipation (given RθJA = 156.2°C/W) leads the expected junction temperature to exceed the absolute maximum of 150°C, the power dissipation must be reduced accordingly.

As the effective FIT rate is highly dependent on the power dissipation of the device, a different FIT rate table is presented for each of the RES11A-Q1 ratios available. Estimated FIT rates are provided for cases where 100%, 80%, 60%, 40%, and 20% of the maximum allowed power dissipation is utilized.