Answers to Common Sigma-Delta ADC Questions on MSP MCUs

Abstract

Sigma-Delta (also referred to as Delta-Sigma) analog-to-digital converters (ADCs) are typically used in analog sensing and measurement applications where a high resolution is preferred over a fast sampling frequency. However, these ADCs are not as well-known as successive approximation register (SAR) ADCs, so designers may face more challenges using them. While TI offers various discrete ADCs, several MSP430™ microcontrollers (MCUs) feature integrated Sigma-Delta ADCs. This application report demystifies these Sigma-Delta ADCs by briefly explaining how they work in real-world applications, comparing their key features and addressing common challenges. To learn more about these ADCs in general, watch the Designing with Delta-Sigma ADCs training series. For more information, see the device-specific data sheet and user's guide.

Trademarks

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1 Introduction: MSP Sigma-Delta ADCs and Common Applications

Several MSP430™ MCU families such as MSP430AFE2xx, MSP430F67xxA and MSP430i20xx feature integrated 24-bit Sigma-Delta (SD) ADC modules whereas other legacy families such as MSP430F42x, MSP430F47x and MSP430F20x3 feature 16-bit SD ADC modules with lower performance and fewer features. This document focuses mainly on the devices with 24-bit SD ADC modules, but it can also be used as a reference for the legacy devices.

Compared to a discrete solution, these MSP430 MCUs enable high-accuracy applications such as passive infrared (PIR) motion detectors with single sensors or small arrays, infrared (IR) thermometers, revenue-grade electricity meters and solar inverters by combining high-performance analog with digital modules as a system-on-chip (SoC) solution that requires fewer external components and less board space.

2 MSP Sigma-Delta ADC Portfolio

Table 2-1 compares the key features of the SD ADC modules available on MSP430 MCUs.

Table 2-1 MSP Sigma-Delta ADC Feature Comparison

Parameter	SD16	SD16_A	CTSD16	SD24_A	SD24_B	SD24	SDHS
MSP430 device families	F(E)42x(A)	F20x3 F(G)42x0 F(G)47x F47(1)xx	FG6x2x	AFE2xx	F67xx(1)(A)	i20xx	FR50xx FR60xx
Number of independent ADCs (referred to as channels) ⁽¹⁾	1, 3	1, 3, 4, 6, 7	1	1, 2, 3	2, 3, 4, 6, 7	2, 3, 4	1
Modulator frequency range	0.5 to 1 MHz	0.03 to 1.1 MHz	1.024 MHz	0.03 to 1.1 MHz	0.03 to 2.3 MHz	1.024 MHz	68 to 80 MHz
Oversampling rate (OSR) range	32 to 256	32 to 1024	32 to 256	32 to 1024	1 to 1024	32 to 256	10 to 160
Maximum ADC sampling frequency (data rate)	31.25 kHz	34.375 kHz	32 kHz	34.375 kHz	2.3 MHz ⁽²⁾	32 kHz	8 MHz
Maximum full-scale range (FSR)	±500 mV	±500 mV	±928 mV	±500 mV	±930 mV	±928 mV	±500 mV
Programmable gain amplifier (PGA) range	1 to 32	1 to 32	1 to 16	1 to 32	1 to 128	1 to 16	0.5 to 34.5
Internal short for PGA offset measurement	YES	YES	YES	YES	YES	NO	NO
Integrated buffer(s)	NO	YES⁽³⁾	YES	NO	NO	NO	NO
Grouped ADC channels	YES	YES ⁽³⁾	YES	YES	YES	YES	NO
Synchronization with external modules (for example, SAR ADC)	NO	NO	NO	NO	YES	NO	NO
Modulator order	Second-order	Second-order	Second-order	Second-order	Second-order	Second-order	Third-order
Type of digital filter(s)	SINC³	SINC³	SINC³	SINC³	SINC³	SINC³	CIC⁷ (stage 1) CIC¹ (stage 2)
Architecture	Discrete-Time	Discrete-Time	Continuous-Time	Discrete-Time	Discrete-Time	Continuous-Time	Discrete-Time

(1) Number of ADC channels is device dependent.

(2) This sampling frequency is a theoretical maximum and will probably not generate meaningful results.

(3) Not implemented on all devices. For more information, see the device-specific data sheet.

3 Sigma-Delta ADC Overview

Analog-to-digital converters do just that: they convert real-world signals into an abstract representation for digital processing. There are several different ADC architectures including slope, pipeline, SAR and SD. Each architecture has its advantages and disadvantages. For example, SAR ADCs typically support higher throughput but lower resolution than SD ADCs. Also, SD ADCs support negative input voltages whereas most SAR ADCs do not. While this application report focuses on SD ADCs, watch Part 1 of the Choosing the Best ADC Architecture for Your Application training series to learn more about different ADC architectures.

A typical Sigma-Delta (also referred to as Delta-Sigma) ADC is shown in Figure 3-1 and includes two main components: the modulator and the decimation filter. At a high level, the modulator functions as the analog front end that samples the analog input signal and then converts it into a modulated digital bit stream which gets fed into the decimation filter. The decimation filter includes a digital filter that converts the bit stream into an oversampled digital representation of the analog signal and a decimator that undersamples that result to produce the digital output.

Figure 3-1 Typical Sigma-Delta ADC Block Diagram

To learn more about how SD ADCs work, watch Part 3 and Part 4 of the Choosing the Best ADC Architecture for Your Application training series. Also, see the device-specific data sheet and user's guide.