SLAA957 September   2020 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2003 , MSP430F2013 , MSP430F2013-EP , MSP430F423A , MSP430F4250 , MSP430F425A , MSP430F4260 , MSP430F4270 , MSP430F427A , MSP430F47126 , MSP430F47127 , MSP430F47163 , MSP430F47166 , MSP430F47167 , MSP430F47173 , MSP430F47176 , MSP430F47177 , MSP430F47183 , MSP430F47186 , MSP430F47187 , MSP430F47193 , MSP430F47196 , MSP430F47197 , MSP430F477 , MSP430F478 , MSP430F4783 , MSP430F4784 , MSP430F479 , MSP430F4793 , MSP430F4794 , MSP430F6720 , MSP430F6720A , MSP430F6721 , MSP430F6721A , MSP430F6723 , MSP430F6723A , MSP430F6724 , MSP430F6724A , MSP430F6725 , MSP430F6725A , MSP430F6726 , MSP430F6726A , MSP430F6730 , MSP430F6730A , MSP430F6731 , MSP430F6731A , MSP430F6733 , MSP430F6733A , MSP430F6734 , MSP430F6734A , MSP430F6735 , MSP430F6735A , MSP430F6736 , MSP430F6736A , MSP430F6745 , MSP430F67451 , MSP430F67451A , MSP430F6745A , MSP430F6746 , MSP430F67461 , MSP430F67461A , MSP430F6746A , MSP430F6747 , MSP430F67471 , MSP430F67471A , MSP430F6747A , MSP430F6748 , MSP430F67481 , MSP430F67481A , MSP430F6748A , MSP430F6749 , MSP430F67491 , MSP430F67491A , MSP430F6749A , MSP430F67621 , MSP430F67621A , MSP430F67641 , MSP430F67641A , MSP430F6765 , MSP430F67651 , MSP430F67651A , MSP430F6765A , MSP430F6766 , MSP430F67661 , MSP430F67661A , MSP430F6766A , MSP430F6767 , MSP430F67671 , MSP430F67671A , MSP430F6767A , MSP430F6768 , MSP430F67681 , MSP430F67681A , MSP430F6768A , MSP430F6769 , MSP430F67691 , MSP430F67691A , MSP430F6769A , MSP430F6775 , MSP430F67751 , MSP430F67751A , MSP430F6775A , MSP430F6776 , MSP430F67761 , MSP430F67761A , MSP430F6776A , MSP430F6777 , MSP430F67771 , MSP430F67771A , MSP430F6777A , MSP430F6778 , MSP430F67781 , MSP430F67781A , MSP430F6778A , MSP430F6779 , MSP430F67791 , MSP430F67791A , MSP430F6779A , MSP430FE423 , MSP430FE4232 , MSP430FE423A , MSP430FE4242 , MSP430FE425 , MSP430FE4252 , MSP430FE425A , MSP430FE427 , MSP430FE4272 , MSP430FE427A , MSP430FG4250 , MSP430FG4260 , MSP430FG4270 , MSP430FG477 , MSP430FG478 , MSP430FG479 , MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626 , MSP430FR5041 , MSP430FR5043 , MSP430FR50431 , MSP430FR6005 , MSP430FR6007 , MSP430FR6041 , MSP430FR6043 , MSP430FR60431 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471 , MSP430I2020 , MSP430I2021 , MSP430I2030 , MSP430I2031 , MSP430I2040 , MSP430I2041

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction: MSP Sigma-Delta ADCs and Common Applications
  4. 2MSP Sigma-Delta ADC Portfolio
  5. 3Sigma-Delta ADC Overview
  6. 4MSP Sigma-Delta ADC Features
    1. 4.1  ADC Inputs: Differential or Single-Ended
    2. 4.2  Input Channels: Independent or Multiplexed
    3. 4.3  Integrated Buffers
    4. 4.4  Integrated PGAs
    5. 4.5  Offset Calibration: Internal or External
    6. 4.6  Voltage Reference: Internal or External
    7. 4.7  ADC Modulator Clock Frequency: Fixed or Adjustable
    8. 4.8  Sampling Rate versus Data Rate
    9. 4.9  Conversion Mode: Single or Continuous
    10. 4.10 Groups of ADC Channels
    11. 4.11 Preload
    12. 4.12 Output Format: Unipolar or Bipolar Data
    13. 4.13 Module Synchronization
    14. 4.14 Architecture: Discrete-Time versus Continuous-Time
  7. 5Solutions to Common MSP Sigma-Delta ADC Configuration Issues
    1. 5.1 ADC Input Configuration
      1. 5.1.1 Settling Time Exceeds Recommended Minimum
      2. 5.1.2 Amplitude of the Input Signal Exceeds FSR
      3. 5.1.3 Missing Anti-Aliasing Filters
    2. 5.2 ADC Clocking Configuration
      1. 5.2.1 Incorrect Sampling Frequency
    3. 5.3 ADC Results
      1. 5.3.1 Unexpected Output Data Format
      2. 5.3.2 Low Resolution
      3. 5.3.3 Data Interpretation
    4. 5.4 Reference Module (REF) Configuration
      1. 5.4.1 Choosing Between an Internal or External Reference
      2. 5.4.2 Connecting the Recommended Capacitors
      3. 5.4.3 Delaying Conversions Until the Reference Settles
    5. 5.5 Hardware Recommendations
  8. 6Frequently Asked Questions
  9. 7References

4.11 Preload

Preload represents a fractional-sample delay between ADC conversions. When the preload value for each channel is applied, the next ADC conversion is delayed by a specific number of modulator clock cycles that can range from zero (no delay) to OSR minus one (nearly a whole-sample delay). Also, the delay is cumulative - the initial preload value and any subsequent preload values add up creating a total delay. When that value exceeds OSR minus one, the total delay rolls over. Whole-sample delays must be implemented in software. For a group of channels that are started simultaneously, the preload for each channel can be adjusted independently to align periodic (AC) signals. However, it is easier to stop the conversions, update the preload values and then restart the conversions rather than tracking the preload applied to each channel. Note that preload is not necessary for aperiodic (DC) signals. For more details about how to use preload, see the device-specific user's guide.