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  1.   Abstract
  2.   Trademarks
  3. 1Introduction: MSP Sigma-Delta ADCs and Common Applications
  4. 2MSP Sigma-Delta ADC Portfolio
  5. 3Sigma-Delta ADC Overview
  6. 4MSP Sigma-Delta ADC Features
    1. 4.1  ADC Inputs: Differential or Single-Ended
    2. 4.2  Input Channels: Independent or Multiplexed
    3. 4.3  Integrated Buffers
    4. 4.4  Integrated PGAs
    5. 4.5  Offset Calibration: Internal or External
    6. 4.6  Voltage Reference: Internal or External
    7. 4.7  ADC Modulator Clock Frequency: Fixed or Adjustable
    8. 4.8  Sampling Rate versus Data Rate
    9. 4.9  Conversion Mode: Single or Continuous
    10. 4.10 Groups of ADC Channels
    11. 4.11 Preload
    12. 4.12 Output Format: Unipolar or Bipolar Data
    13. 4.13 Module Synchronization
    14. 4.14 Architecture: Discrete-Time versus Continuous-Time
  7. 5Solutions to Common MSP Sigma-Delta ADC Configuration Issues
    1. 5.1 ADC Input Configuration
      1. 5.1.1 Settling Time Exceeds Recommended Minimum
      2. 5.1.2 Amplitude of the Input Signal Exceeds FSR
      3. 5.1.3 Missing Anti-Aliasing Filters
    2. 5.2 ADC Clocking Configuration
      1. 5.2.1 Incorrect Sampling Frequency
    3. 5.3 ADC Results
      1. 5.3.1 Unexpected Output Data Format
      2. 5.3.2 Low Resolution
      3. 5.3.3 Data Interpretation
    4. 5.4 Reference Module (REF) Configuration
      1. 5.4.1 Choosing Between an Internal or External Reference
      2. 5.4.2 Connecting the Recommended Capacitors
      3. 5.4.3 Delaying Conversions Until the Reference Settles
    5. 5.5 Hardware Recommendations
  8. 6Frequently Asked Questions
  9. 7References

4.3 Integrated Buffers

Depending on the device, the SD16_A and CTSD16 modules in Table 2-1 feature integrated buffers. In applications that require high-impedance external circuits (for example, high-order passive filters), these buffers help prevent the external circuit from impacting the ADC's minimum settling time.