SLAAEF9 November 2023 MSPM0C1104 , MSPM0G3507 , MSPM0L1306
Unlike RL78 devices, MSPM0 devices set the priority level of each peripheral interrupt source through the IPRx registers in the NVIC, and mask/unmask a peripheral interrupt source through ISER and ICER register in the NVIC. Each peripheral interrupt contains kinds of interrupt conditions. For example, as a peripheral interrupt source, UARTx has multiple interrupt conditions such as transmit interrupt and receive interrupt, and so forth. And the interrupt conditions are managed by six standard registers in the peripheral side.
Figure 3-3 shows the peripheral interrupt hierarchy.