SLAAEK4 January   2024 MSPM0C1104

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Comparison Between TIMA and TIMG
  6. 3 Use Case - 3 Pairs of Complementary PWM with Deadband Insertion
    1. 3.1 Principle
    2. 3.2 Implement
  7. 4 Use Case - Timing-Critical PWM Control with Shadow Load and Compare
    1. 4.1 Principle
    2. 4.2 Implement
  8. 5 Use Case - Fault Handler
    1. 5.1 Principle
    2. 5.2 Implement
  9. 6 Use Case – PWM Disable with Software Force Output
    1. 6.1 Principle
    2. 6.2 Implement
  10. 7 Use Case - Asymmetric PWM
    1. 7.1 Principle
    2. 7.2 Implement
  11. 8 Use Case – Optimal Interrupt Generation with Repeat Counter
    1. 8.1 Principle
    2. 8.2 Implement
  12. 9 Summary
  13. 10References

5.2 Implement

Before configuring fault handler, it is important to consider the following basic properties of faults in a system, such as:

  • Fault input selection (fault signal from external IC, internal signal, and so on)
  • How long a fault condition lasts, or the fault condition duration
  • How the counter reacts to the entry and exit of a fault condition
  • How the output signal reacts to the entry and exit of a fault condition

For fault input source, the user can select the polarity and enable various fault input sources, such as comparator (COMP) output, external fault pin, system clock fault or a trigger. The user can also controls the input filtering for the fault input.

  • The comparator output is useful for fault detection when COMPs are used for detecting overcurrent or overvoltage events.
  • There are 3 fault external signal pins can be used to detect the fault condition outside the MCU.
  • Any system clock fault can be used to trigger the PWM output to a Hi-Z state.
  • A trigger can be configured to generate a fault condition is detected. This is useful for performing diagnostics or creating fault dependencies from other peripherals in the event fabric.

Fault handler can have effects on counter and output. For counter behavior with fault conditions, counter can be set to stop immediately, stop when reaches zero or continue to count. Upon exit of fault mode, the counter can be set to restart from Load value, 0 value, or continue counting from where it left off. Figure 8-9shows the counter behavior in fault condition with different configurations.

For output behavior with fault conditions, the CCP output value can be set high, set low, toggled, tristated (Hi-Z), or unaffected by the fault event.

GUID-5B97F906-807D-4184-99EB-F73EAC1AAD65-low.svg Figure 5-1 Counter Behavior in Fault Condition

To accelerate development, please refer to the following resources.