SLASEJ5B October   2017  – January 2020

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Gated Output (Gx)
      3. 7.3.3 Register Clear (CLR)
      4. 7.3.4 Open-Drain Outputs and Flexible Diagnostics Channel
        1. 7.3.4.1 Configurable Outputs
        2. 7.3.4.2 LED-Open Diagnostics
        3. 7.3.4.3 LED-Short Diagnostics
      5. 7.3.5 Thermal Shutdown
      6. 7.3.6 Command Error
      7. 7.3.7 Serial Communication Error
      8. 7.3.8 Error Feedback
      9. 7.3.9 Interface
        1. 7.3.9.1 Register Write
        2. 7.3.9.2 Register Read
        3. 7.3.9.3 Shift-Register Communication-Fault Detection
        4. 7.3.9.4 Clear Register
        5. 7.3.9.5 Register Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 POR Reset
      3. 7.4.3 Standby Mode
    5. 7.5 Register Maps
    6. 7.6 Interface Registers
      1. 7.6.1 Configuration Register (Offset = 0h) [reset = 0h]
        1. Table 5. Configuration Register Field Descriptions
      2. 7.6.2 Fault Readback Register (Offset = 1h) [reset = 0h]
        1. Table 6. Fault Readback Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.6 Interface Registers

Table 3 lists the memory-mapped registers for the interface.

Table 3. Interface Registers

OFFSET ACRONYM REGISTER NAME SECTION
0h Config Configuration Register Go
1h Fault_Readback Fault Readback Register Go

Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for access types in this section.

Table 4. Interface Access Type Codes

CODE DESCRIPTION
Read type R Read-only
Read to clear RC Read to clear the fault
Write type W Write-only
Reset or Default Value -n Value after reset or the default value