SLAU640B April   2019  – March 2023 ADC12DJ5200SE

 

  1.   Introduction
  2. 1Trademarks
  3. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  4. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the EVM and TSW14J57EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)
    6. 3.6  Turn On the TSW14J57EVM Power and Connect to the PC
    7. 3.7  Turn On the ADC12DJ5200RFEVM/SEEVM Power Supplies and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the ADC12DJ5200RFEVM/SEEVM GUI and Program the ADC and Clocks
    10. 3.10 Calibrate the ADC Device on the EVM
    11. 3.11 Open the HSDC Software and Load the FPGA Image to the TSW14J57EVM
    12. 3.12 Capture Data Using the HSDC Pro Software
  5. 4Device Configuration
    1. 4.1 Supported JESD204C Device Features
    2. 4.2 Tab Organization
    3. 4.3 Low-Level Control
  6. 5Troubleshooting the ADC12DJ5200RFEVM/SEEVM
  7. 6References
    1. 6.1 Technical Reference Documents
    2. 6.2 TSW14J57EVM Operation
  8. 7HSDC Pro Settings for Optional ADC Device Configuration
    1. 7.1 Changing the Number of Frames per Multi-Frame (K)
    2. 7.2 Customizing the EVM for Optional Clocking Support
      1. 7.2.1 External Clocking Option (Default)
      2. 7.2.2 Onboard Clocking Option
      3. 7.2.3 External Reference Clocking Option
  9. 8Signal Routing
    1. 8.1 Signal Routing
  10.   A Analog Inputs
  11.   B Jumpers and LEDs
    1. 10.1 Jumper settings
  12.   B Revision History

7.2.1 External Clocking Option (Default)

By default, the EVM is configured to use the external clock option. The user provide and external clock signal for both the ADC sampling clock(DEVCLK at J10) and also the Reference clock(REF CLK at J17) which feed into the LMK04828 and is used in clock distribution mode and provides the FPGA reference clock, FPGA SYSREF signal and ADC SYSREF signal. If coherent sampling is desired the external clocking has to be used. #T4706554-2 shows the block diagram of external clocking option:

The EVM can be configured to use external clocks with the following steps (see GUID-3F838D4C-C2E8-49DE-A0A7-58037FB663BD.html#SLAU7018586):

  1. Modify the hardware:
    1. Remove R171 and R174, populate C2 and C3.
    2. Remove C52 and C306, populate C60 and C61
    3. Install Jumper J13

GUID-E35F8DEE-80BF-482A-8F2E-4C78034B78B5-low.gifFigure 7-1 ADC12DJ5200RFEVM/SEEVM Clocking System Block Diagram