SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 18-10 lists the memory-mapped registers for the GPTM. All register offset addresses not listed in Table 18-10 should be considered as reserved locations and the register contents should not be modified.
The offset listed is relative to base address of each timer:
The GP Timer module clock must be enabled before the registers can be programmed (see Section 4.2.86). There must be a delay of 3 system clock cycles after the Timer module clock is enabled before any Timer module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | GPTMCFG | GPTM Configuration | Section 18.5.1 |
| 0x4 | GPTMTAMR | GPTM Timer A Mode | Section 18.5.2 |
| 0x8 | GPTMTBMR | GPTM Timer B Mode | Section 18.5.3 |
| 0xC | GPTMCTL | GPTM Control | Section 18.5.4 |
| 0x10 | GPTMSYNC | GPTM Synchronize | Section 18.5.5 |
| 0x18 | GPTMIMR | GPTM Interrupt Mask | Section 18.5.6 |
| 0x1C | GPTMRIS | GPTM Raw Interrupt Status | Section 18.5.7 |
| 0x20 | GPTMMIS | GPTM Masked Interrupt Status | Section 18.5.8 |
| 0x24 | GPTMICR | GPTM Interrupt Clear | Section 18.5.9 |
| 0x28 | GPTMTAILR | GPTM Timer A Interval Load | Section 18.5.10 |
| 0x2C | GPTMTBILR | GPTM Timer B Interval Load | Section 18.5.11 |
| 0x30 | GPTMTAMATCHR | GPTM Timer A Match | Section 18.5.12 |
| 0x34 | GPTMTBMATCHR | GPTM Timer B Match | Section 18.5.13 |
| 0x38 | GPTMTAPR | GPTM Timer A Prescale | Section 18.5.14 |
| 0x3C | GPTMTBPR | GPTM Timer B Prescale | Section 18.5.15 |
| 0x40 | GPTMTAPMR | GPTM TimerA Prescale Match | Section 18.5.16 |
| 0x44 | GPTMTBPMR | GPTM TimerB Prescale Match | Section 18.5.17 |
| 0x48 | GPTMTAR | GPTM Timer A | Section 18.5.18 |
| 0x4C | GPTMTBR | GPTM Timer B | Section 18.5.19 |
| 0x50 | GPTMTAV | GPTM Timer A Value | Section 18.5.20 |
| 0x54 | GPTMTBV | GPTM Timer B Value | Section 18.5.21 |
| 0x58 | GPTMRTCPD | GPTM RTC Predivide | Section 18.5.22 |
| 0x5C | GPTMTAPS | GPTM Timer A Prescale Snapshot | Section 18.5.23 |
| 0x60 | GPTMTBPS | GPTM Timer B Prescale Snapshot | Section 18.5.24 |
| 0x6C | GPTMDMAEV | GPTM DMA Event | Section 18.5.25 |
| 0x70 | GPTMADCEV | GPTM ADC Event | Section 18.5.26 |
| 0xFC0 | GPTMPP | GPTM Peripheral Properties | Section 18.5.27 |
| 0xFC8 | GPTMCC | GPTM Clock Configuration | Section 18.5.28 |
Complex bit access types are encoded to fit into small table cells. Table 18-11 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |