4.1.5.2.1.3.2 MII Interface Clocking
Four clock inputs are driven into the Ethernet MAC when the MII configuration is enabled. The clocks are described as follows (see Section 15.3.1.2 for more information):
- Gated system clock (SysClk): The SysClk signal acts as the clock source to the CSRs of the Ethernet MAC. The SysClk frequency for run, sleep, and deep-sleep modes is programmed in the System Control module.
- MOSC: A gated version of the MOSC clock is provided as the Precision Time Protocol (PTP) reference clock (PTPREF_CLK). The MOSC clock source can be a single-ended source on the OSC0 pin or a crystal on the OSC0 and OSC1 pins. When advanced timestamping is used and the PTP module has been enabled by setting the PTPCEN bit in the EMACCC register, the MOSC drives PTPREF_CLK. PTPREF_CLK has a minimum frequency requirement of 5 MHz and a maximum frequency of 25 MHz. See Section 15.3.6 for more information.
- EN0RXCK: This clock signal is driven by the external PHY oscillator and is either 2.5 or 25 MHz depending on whether the device is operating at 10 or 100 Mbps.
- EN0TXCK: This clock signal is driven by the external PHY oscillator and is either 2.5 or 25 MHz depending on whether the device is operating at 10 or 100 Mbps.