SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers are configured as an up-counter. When RTC mode is selected for the first time after reset, the counter is loaded with a value of 0x1. All subsequent load values must be written to the GPTM Timer n Interval Load (GPTMTnILR) registers (see Section 18.5.10). If the GPTMTnILR register is loaded with a new value, the counter begins counting at that value and rolls over at the fixed value of 0xFFFFFFFF. Table 18-5 lists the values that are loaded into the timer registers when the timer is enabled.
| Register | Count Down Mode | Count Up Mode |
|---|---|---|
| GPTMTnR | Not available | 0x1 |
| GPTMTnV | Not available | 0x1 |
| GPTMTnPS | Not available | Not available |
The input clock on a CCP 0 input must be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1-Hz rate and passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from its preloaded value of 0x1. When the current count value matches the preloaded value in the GPTMTnMATCHR registers, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
In addition to generating interrupts, the RTC can generate a µDMA trigger. The µDMA trigger is enabled by configuring and enabling the appropriate µDMA channel as well as the type of trigger enable in the GPTM DMA Event (GPTMDMAEV) register (see Section 8.3.4).