SLAU863 October   2021 ADC12DJ4000RF , ADC12DJ5200RF , TRF1208

 

  1.   Trademarks
  2. 1Features
  3. 2Equipment
    1. 2.1 Evaluation Board Feature Identification Summary
    2. 2.2 Required Equipment
  4. 3Setup Procedure
    1. 3.1  Install the High Speed Data Converter (HSDC) Pro Software
    2. 3.2  Install the Configuration GUI Software
    3. 3.3  Connect the EVM and TSW14J57EVM
    4. 3.4  Connect the Power Supplies to the Boards (Power Off)
    5. 3.5  Connect the Signal Generators to the EVM (Signal Generator's RF Outputs Disabled Until Directed)
      1. 3.5.1 When External Clocking is Used
    6. 3.6  Turn On the TSW14J57EVM Power and Connect to the PC
    7. 3.7  Turn On the ADCxxDJxx00RF-TRF1208-EVM Power Supplies and Connect to the PC
    8. 3.8  Turn On the Signal Generator RF Outputs
    9. 3.9  Open the ADC12DJ5200RFEVM GUI and Program the ADC and Clocks
    10. 3.10 Calibrate the ADC Device on the EVM
    11. 3.11 Open the HSDC Software and Load the FPGA Image to the TSW14J57EVM
    12. 3.12 Capture Data Using the HSDC Pro Software
  5. 4Device Configuration
    1. 4.1 Supported JESD204C Device Features
    2. 4.2 Tab Organization
    3. 4.3 Low-Level Control
  6. 5Troubleshooting the ADCxxDJxx00RF-TRF1208-EVM
  7. 6HSDC Pro Settings for Optional ADC Device Configuration
    1. 6.1 Changing the Number of Frames per Multi-Frame (K)
    2. 6.2 Customizing the EVM for Optional Clocking Support
      1. 6.2.1 External Clocking Option (Default)
      2. 6.2.2 Onboard Clocking Option
      3. 6.2.3 External Reference Clocking Option
        1.       31
  8. 7Signal Routing
  9. 8References
    1. 8.1 Technical Reference Documents
    2. 8.2 TSW14J57EVM Operation
  10.   A Analog Inputs
    1.     37
  11.   B Jumpers and LEDs
    1.     10.A Jumper Settings

6.2.3 External Reference Clocking Option

The reference clock(J17) is provided by an external source. The LMK00304 make two copies of the reference signal and sends the one copy to LMX2594 to generate the sampling clock for the ADC and LMK04828 uses the second copy in clock distribution mode to provides the FPGA reference clock, FPGA SYSREF signal. The ADC SYSREF signal is generated by the LMX2594. Figure 6-3 shows the block diagram of external reference clocking option:

The EVM can be configured to use external reference clocking option with the following steps (see Figure 6-5):

  • Remove C2 and C3, populate R171 and R174
  • Remove C60 and C61, populate C52 and C306
  • Install Jumper J13