SLAU934 September   2024 DAC121S101-SEP

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Setup
      1. 2.1.1 Hardware Theory of Operation
      2. 2.1.2 Jumper Definitions
      3. 2.1.3 Connector Definitions
      4. 2.1.4 Test Points
    2. 2.2 Hardware Overview
      1. 2.2.1 Electrostatic Discharge Caution
      2. 2.2.2 Connecting the FTDI Digital Controller
      3. 2.2.3 Glitch Testing
  9. 3Software
    1. 3.1 Software Setup
      1. 3.1.1 Software Installation
    2. 3.2 Software Overview
      1. 3.2.1 Launching the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 Low Level Configuration Page
        2. 3.2.2.2 High Level Configuration Page
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Related Documentation

2.2.3 Glitch Testing

The DAC121S101SEPEVM has dedicated test points for measuring glitch on the VOUT pin. Test point TP10 and capacitor C16 are isolated from the ground and power plane on the EVM. To best measure glitch, remove R16 to isolate the VOUT pin from the rest of the EVM circuitry and populate C16 with the desired capacitive load. A probe can be placed across TP10 and TP12. The glitch measurement taken with the DAC121S101SEPEVM is shown in Figure 2-2. In this example, C12 was populated with a 3.3pF capacitor and the glitch was captured on the rising edge between codes 0x07FF to 0x0800.

DAC121S101SEPEVM Glitch Testing Figure 2-2 Glitch Testing