SLAZ755A May   2024  – October 2024 MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228

ADVANCE INFORMATION  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Functional Advisories
  5. 2Preprogrammed Software Advisories
  6. 3Debug Only Advisories
  7. 4Fixed by Compiler Advisories
  8. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  9. 6Advisory Descriptions
    1. 6.1  ADC_ERR_03
    2. 6.2  ADC_ERR_05
    3. 6.3  ADC_ERR_06
    4. 6.4  COMP_ERR_03
    5. 6.5  COMP_ERR_04
    6. 6.6  GPIO_ERR_03
    7. 6.7  GPIO_ERR_04
    8. 6.8  I2C_ERR_03
    9. 6.9  I2C_ERR_05
    10. 6.10 I2C_ERR_06
    11. 6.11 LFXT_ERR_01
    12. 6.12 LFXT_ERR_02
    13. 6.13 PMCU_ERR_07
    14. 6.14 PMCU_ERR_08
    15. 6.15 PMCU_ERR_10
    16. 6.16 PMCU_ERR_12
    17. 6.17 RTC_A_ERR_02
    18. 6.18 SPI_ERR_03
    19. 6.19 SPI_ERR_04
    20. 6.20 SPI_ERR_05
    21. 6.21 SRAM_ERR_01
    22. 6.22 SYSOSC_ERR_01
    23. 6.23 TAMPERIO_ERR_01
    24. 6.24 TIMER_ERR_01
    25. 6.25 TIMER_ERR_04
    26. 6.26 UART_ERR_01
    27. 6.27 UART_ERR_02
    28. 6.28 UART_ERR_03
    29. 6.29 VREF_ERR_03
  10. 7Revision History

6.22 SYSOSC_ERR_01

SYSOSC Module

Category

Functional

Function

MFCLK drift when using SYSOSC FCL together with STOP1 mode

Description

IF MFCLK is enabled AND SYSOSC is using the frequency correction loop (FCL) mode AND the STOP1 low power operating mode is used, THEN the MFCLK may drift by two cycles when SYSOSC shifts from 4MHz back to 32MHz (either upon exit from STOP1 to RUN mode or upon an asynchronous fast clock request that forces SYSOSC to 32MHz).

Workaround


Use STOP0 mode instead of STOP1 mode. There is no MFCLK drift when STOP0 mode is used.

OR

Do not use SYSOSC in the FCL mode (leave FCL disabled) when using STOP1.