SLLA521B January 2022 – June 2022 TCAN1145-Q1 , TCAN1146-Q1
Parameter | Example Value |
---|---|
Desired WUF ID | Standard ID (11-bit) 0x122/123 |
ID Mask | 0×001 (Match all bits except bit 0, 1 = Disregard, 0 = must match) |
Bus arbitration rate/CAN FD rate | 500 kbps/2 Mbps |
Ignore CAN FD | True |
WUF DLC | 2 Byte (DLC: 0×2) |
WUF Data bits to wake up to | Byte 0[1], Byte 1[7] |
Breaking down the example parameter values, the WUF ID is 0×123 or 0×122. The value written into the register does not matter which of the two is entered, since the ID mask will be used to mark bit 0 as disregard. By setting bit 0 of the ID mask to a 1, we tell the device to ignore this bit, which means it will accept a 0×122 or 0×123 ID. The CAN FD bus in this example has an arbitration and data rate of 500 kbps and 2 Mbps respectively. Since this theoretical bus is a CAN FD bus, we want to allow regular CAN FD traffic to occur while some nodes are asleep, so SW_PASSIVE is set to 1b.
A change for this example is to do some verification against the data payload. Note that data payload checking will require an exact match for the DLC, but the way a WUF data bit is checked is bit-wise OR only. For example, the bits that are set to 1 are checked against the payload and will be considered a match if any single bit (or more) match. Likewise, if a WUF data mask is set to 0×FF, then any value with a bit equal to 1 will be matched. If a WUF data mask is set to 0×00, then that particular byte is essentially ignored, and cannot be matched, not even if the received data is 0×00. This OR is applied across all configured data bytes (set by the DLC field). Table 5-4 provides an example of how to program the device for this behavior.
Step | Description | Register | Register (Hex) | Data (Hex) | Raw Hex |
---|---|---|---|---|---|
0 | Disable selective wake | SW_CONFIG_4 | 0×47 | 0×00 | 0×8F, 0×00 |
1 | Write desired WUF ID (0×123) | SW_ID1 | 0×30 | 0×00 | 0×61, 0×00 |
2 | Write desired WUF ID (0×123) | SW_ID2 | 0×31 | 0×00 | 0×63, 0×00 |
3 | Write desired WUF ID (0×123) | SW_ID3 | 0×32 | 0×04 | 0×65, 0×04 |
4 | Write desired WUF ID (0×123) | SW_ID4 | 0×33 | 0×8C | 0×67, 0×8C |
5 | Write ID mask to (0×001) SW_ID_MASK1 | SW_ID_MASK1 | 0×34 | 0×00 | 0×69, 0×00 |
6 | Write ID mask to (0×001) SW_ID_MASK2 | SW_ID_MASK2 | 0×35 | 0×00 | 0×6B, 0×00 |
7 | Write ID mask to (0×001) SW_ID_MASK3 | SW_ID_MASK3 | 0×36 | 0×00 | 0×6D, 0×00 |
8 | Write ID mask to (0×001) SW_ID_MASK4 | SW_ID_MASK4 | 0×37 | 0×00 | 0×6F, 0×00 |
9 | Write ID mask (0×001), DLC (2), and DATA_MASK_EN (1) | SW_ID_MASK_DLC | 0×38 | 0×25 | 0×71, 0×25 |
10 | Write Data 0 (0×01) | DATA_0 | 0×39 | 0×01 | 0×73, 0×01 |
11 | Write Data 1 (0×80) | DATA_1 | 0×40 | 0×80 | 0×75, 0×80 |
12 | Configure arbitration speed, FD:CAN ratio, and SW_FD_PASSIVE (1) | SW_CONFIG_1 | 0×44 | 0×D0 | 0×89, 0×D0 |
13 | Set frame overflow to 255 (maximum number of errors before wake up) | SW_CONFIG_3 | 0×46 | 0×FE | 0×8D, 0×FE |
14 | Set SWCFG bit (configuration is complete) | SW_CONFIG_4 | 0×47 | 0×80 | 0×8F,0×80 |
15 | Enable selective wake and go to sleep | MODE_CNTRL | 0×10 | 0×81 | 0×21, 0×81 |