The TLIN1431x-Q1 has an integrated watchdog function and provides two watchdog types that can be set up when using SPI control: window watchdog or timeout watchdog. If more frequent (i.e. <16 ms) input trigger events are desired it is suggested to us the timeout watchdog. When using timeout watchdog, the input trigger can occur anywhere before the timeout and is not tied to an open window. The device defaults to window watchdog at power up but can be programmed to support timeout watchdog. The watchdog registers for input trigger and configuration are located at 8'h13 through 8'h16. WD_CONFIG_1 register 8'h13[7:4] and WD_CONFIG_2 register 8'h14[7:5] are used to set up timing. See Table 6-6 for available watchdog timing.

When using the window watchdog, it is important to understand the closed and open window aspects. The device is set up with a 50%/50% open and closed window and is based on an internal oscillator with a ± 10% accuracy range. To determine when to provide the input trigger, this variance needs to be considered. For example, using the 64 ms nominal total window provides a closed and open window that are each 32 ms. Taking the ±10% internal oscillator into account means the total window could range from 57.6 ms to 70.4 ms. The closed and open window could then range from 22.4 ms to 35.2 ms. From the 57.6 ms total window and 35.2 ms closed window, the total open window is 22.4 ms. The trigger event needs to happen at 46.4 ms ± 11.2 ms. See Figure 6-6 for when the initial window is needed and when the device would expect a watchdog input trigger for a window watchdog configuration. See Figure 6-7 and Figure 6-8 for state diagrams on how the WD behaves.

The TLIN1431x-Q1 has a watchdog error counter used in SPI control mode. This counter is an up down counter that increments for every missed window or incorrect input watchdog trigger event. In SPI control, the error counter is set at one by default. The counter decrements for every correct input trigger and increments on every incorrect input trigger, but it never drops below zero. When the programmed counter is reached, the device transitions to restart mode and pulls nRST pin low for t_{NRST_TOG}. At the end of this time, the device transitions back to standby mode releasing the nRST pin to high. This counter can be changed to 1 (every error), 9, or 15 using 8'h16[7:6]. The error counter can be read at register 8'h14[4:1]. In pin control, nWDR is pulled low for every watchdog error.

If the watchdog error count is set at one, the first input failure causes the device to transition to restart. This allows the system to check the counter after the first input trigger to see if a valid input was sent. Every incorrect watchdog input causes the interrupt to be set and nINT is pulled low.

The LIMP pin provides a limp home capability when connected to external circuitry. When in sleep mode, the LIMP pin is off. When the error counter reaches the watchdog trigger event level, the LIMP pin turns on connecting VSUP to the pin as described in the LIMP pin section.