SLLSE41H June   2010  – March 2016 SN75LVCP601

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power Dissipation Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Jitter and VOD Results: Case 1 at 6 Gbps
    2. 7.2 Jitter and VOD Results: Case 2 at 3 Gbps
    3. 7.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Equalization
      2. 8.3.2 Output De-Emphasis
      3. 8.3.3 Out-of-Band (OOB) Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Equalization Configuration
        2. 9.2.2.2 De-emphasis Configuration
      3. 9.2.3 Application Curves
        1. 9.2.3.1 SN75LVCP601 Equalization Settings For Various Input Trace Lengths
        2. 9.2.3.2 SN75LVCP601 De-emphasis Settings For Various Output Trace Lengths
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RTJ Package
16-Pin WQFN With Thermal Pad
SN75LVCP601 POs_llse41.gif

Pin Functions

PIN PIN TYPE DESCRIPTION
NAME NO.
CONTROL PINS
DE1(1) 9 I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
DE2(1) 8
DEW1 16 I, LVCMOS De-emphasis width control for CH 1 and CH 2.
0 = De-emphasis pulse duration, short
1 = De-emphasis pulse duration, long (default)
DEW2 6
EN 7 I, LVCMOS Device enable and disable pin, internally pulled to VCC.
0 = Device in standby mode
1 = Device enabled (default)
EQ1(1) 17 I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 1.
Internally tied to VCC / 2.
EQ2(1) 19
HIGH-SPEED DIFFERENTIAL I/O
RX1N 2 I, CML Noninverting and inverting CML differential input for CH 1 and CH 2. These pins connect to an internal voltage bias via a dual-termination resistor circuit.
RX1P 1 I, CML
RX2N 12 I, CML
RX2P 11 I, CML
TX1N 14 O, VML Noninverting and inverting VML differential output for CH 1 and CH 2. These pins connect internally to voltage bias via termination resistors.
TX1P 15 O, VML
TX2N 4 O, VML
TX2P 5 O, VML
POWER
GND 3, 13, 18 Power Supply ground
VCC 10, 20 Power Positive supply must be 3.3 V ± 10%
(1) Internally biased to VCC / 2 with >200-kΩ pullup or pulldown. When 3-state pins are left as NC, board leakage at the pin pad must be <1 µA; otherwise, drive to VCC / 2 to assert mid-level state.