SLLSFC2D December   2020  – September 2021 ISO1642 , ISO1643 , ISO1644

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Supply Current Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 I2C Switching Characteristics
    13. 6.13 GPIO Switching Characteristics
    14. 6.14 Insulation Characteristics Curves
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Isolation Technology Overview
    4. 8.4 Feature Description
      1. 8.4.1 Hot Swap
      2. 8.4.2 Protection Features
      3. 8.4.3 GPIO Channels
    5. 8.5 Isolator Functional Principle
      1. 8.5.1 Receive Direction (Left Diagram of Figure 1-1 )
      2. 8.5.2 Transmit Direction (Right Diagram of Figure 1-1 )
    6. 8.6 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I2C Bus Overview
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.12 I2C Switching Characteristics

over recommended operating conditions, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V
tf2 Output signal fall time
(SDA2 and SCL2)		 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 72 Ω,
C2 = 400 pF, see Figure 7-1 		16 26.5 40 ns
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 72Ω,
C2 = 400 pF, see Figure 7-1 		38 53.3 78
tpLH1-2 Low-to-high propagation delay, side 1 to side 2 VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Figure 7-1 20 30 ns
tpHL1-2 High-to-low propagation delay, side 1 to side 2 VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Figure 7-1 80 130 ns
tpLH2-1 Low-to-high propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Figure 7-1 40 48 ns
tpHL2-1 High-to-low propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Figure 7-1 70 100 ns
PWD1-2 Pulse width distortion
|tpHL1-2 – tpLH1-2|		 R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V
see Figure 7-1 		60 104 ns
PWD2-1 Pulse width distortion(1)
|tpHL2-1 – tpLH2-1|		 R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V
see Figure 7-1 		25 55 ns
tLOOP1 Round-trip propagation delay on side 1(1) 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 72 Ω, C2 = 400 pF, see Figure 7-1 		62 74 ns
3 V ≤ VCC1, VCC2 ≤ 3.6 V
tf1 Output signal fall time
(SDA1 and SCL1)		 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Figure 7-1 		8 17 29 ns
0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 953 Ω,
C1 = 40 pF, see Figure 7-1 		15 25 48
tf2 Output signal fall time
(SDA2 and SCL2)		 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 95.3 Ω,
C2 = 400 pF, see Figure 7-1 		14 23 47 ns
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 95.3 Ω,
C2 = 400 pF, see Figure 7-1 		30 50 100
tpLH1-2 Low-to-high propagation delay, side 1 to side 2 VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Figure 7-1 21 29 ns
tpHL1-2 High-to-low propagation delay, side 1 to side 2 VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Figure 7-1 59 88 ns
tpLH2-1 Low-to-high propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Figure 7-1 40 47 ns
tpHL2-1 High-to-low propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Figure 7-1 70 100 ns
PWD1-2 Pulse width distortion
|tpHL1-2 – tpLH1-2|		 R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF,
see Figure 7-1 		39 61 ns
PWD2-1 Pulse width distortion(1)
|tpHL2-1 – tpLH2-1|		 R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF,
see Figure 7-1 		25 48 ns
tLOOP1 Round-trip propagation delay on side 1(1) 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Figure 7-1 		65 78 ns
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
tf1 Output signal fall time
(SDA1 and SCL1)		 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 1430 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Figure 7-1 		6 16 22 ns
0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 1430 Ω,
C1 = 40 pF, see Figure 7-1 		13 32 48
tf2 Output signal fall time
(SDA2 and SCL2)		 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 143 Ω,
C2 = 400 pF, see Figure 7-1 		10 24 30 ns
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 143 Ω,
C2 = 400 pF, see Figure 7-1 		28 48 76
tpLH1-2 Low-to-high propagation delay, side 1 to side 2 VI = 535 mV, VO = 0.7 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF, see Figure 7-1 21 28 ns
tpHL1-2 High-to-low propagation delay, side 1 to side 2 VI = 550 mV, VO = 0.3 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF, see Figure 7-1 51 70 ns
tpLH2-1 Low-to-high propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF, see Figure 7-1 51 57 ns
tpHL2-1 High-to-low propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF, see Figure 7-1 60 88 ns
PWD1-2 Pulse width distortion
|tpHL1-2 – tpLH1-2|		 R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF,
see Figure 7-1 		30 45 ns
PWD2-1 Pulse width distortion(1)
|tpHL2-1 – tpLH2-1|		 R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF,
see Figure 7-1 		10 34 ns
tLOOP1 Round-trip propagation delay on side 1(1) 0.4 V ≤ VI ≤ 0.3 × VCCI, R1 = 1430 Ω,
C1 = 40 pF, R2 = 143 Ω, C2 = 400 pF, see Figure 7-1 		84 96 ns
(1) This parameter does not apply to the SCL1 line of the ISO1641 device because it is unidirectional.