SLLU312A July   2019  – May 2022 TCAN4550-Q1

 

  1.   TCAN4550-Q1 Functional Safety-Manual
  2.   Trademarks
  3. 1Introduction
  4. 2Product Functional Safety-Capability
  5. 3Product Overview
    1. 3.1 Block Diagram
    2. 3.2 Target Applications
      1. 3.2.1 Diagnostic Features
        1. 3.2.1.1 Mode Overview
        2. 3.2.1.2 Sleep Wake Error Timer (SWE)
        3. 3.2.1.3 Undervoltage
        4. 3.2.1.4 Thermal Shut Down
        5. 3.2.1.5 CAN Bus Communication
          1. 3.2.1.5.1 M_CAN
        6. 3.2.1.6 Processor Communication
          1. 3.2.1.6.1 SPI Integrity
            1. 3.2.1.6.1.1 SPI Scratchpad
            2. 3.2.1.6.1.2 SPIERR
            3. 3.2.1.6.1.3 M_CAN Forced Dominant and Recessive
            4. 3.2.1.6.1.4 SPI and FIFO
            5. 3.2.1.6.1.5 ECC for Memory
          2. 3.2.1.6.2 Timeout Watchdog
          3. 3.2.1.6.3 Floating Pins
          4. 3.2.1.6.4 RST Pin
          5. 3.2.1.6.5 Interrupt and Internal Fault Detection
  6. 4Development Process for Management of Systematic Faults
    1. 4.1 TI New-Product Development Process
  7. 5Revision History
3.2.1.6.1.5 ECC for Memory

The TCAN4550-Q1 provides single bit error correct when writing to and reading from MRAM with the integrated ECC function.

For transmitting; when a message is to be transmitted, the data is read from internal MRAM. If during this read (39 bits at a time for 4-bytes of data), a single bit is flipped, then this bit error is automatically detected and corrected. If 2 bits are flipped, M_CAN exits and does not transmit any data. The device drops into Standby Mode. The M_CAN Bit Error Uncorrected (BEU) interrupt is set. This is an uncorrectable error case. There is no provision for 3+ bits being flipped, but statistically this is considered highly improbable. (3+ error bits could alias into pass, 1, or 2 errors)

For receiving; when a received message is being read through SPI, the data is first fetched from MRAM. If during this read (39 bits at a time), a single bit is flipped, it is corrected. If 2 bits are flipped, an ECCERR interrupt is issued to inform the micro the read is corrupt. The ECCERR should be cleared and the read tried again. There is no provision for 3+ bits flipped. This is the SPI to message RAM ECC error and not be confused with the BEU interrupt in bus communication section.