SLLU367 july   2023 ISO1228

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Pin Configuration of the ISO1228
    2. 2.2 EVM Board Block Diagram and Image
    3. 2.3 EVM Setup and Operation
      1. 2.3.1 EVM Jumper Settings
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials

2.3 EVM Setup and Operation

This section describes the basic setup and operation of the EVM for performance evaluation. Figure 3-3 shows an example of one potential configuration for operating the ISO1228DFBEVM. In this setup, the digital input signal from the signal generator is connected between one of the INx pins and AVSS. The field side power supply is connected at AVCC and AVSS. The logic side power supply is connected at VCC1 and GND1. All output signals are monitored using an oscilloscope on the corresponding OUTx pin.

GUID-20230518-SS0I-N7MR-SSGN-JK0RKK656DDD-low.svg Figure 2-3 Basic EVM Operation
The ISO1228DFBEVM has many "do not populate" (DNP) footprints for components which can be populated to apply different test conditions to the device. Table 3-1 lists and describes all possible test configurations that can be achieved by modifying different components of the EVM.
Table 2-1 Component Configurations
Component Description
D1, D2, D3, D4, D5, D6, D7, D8 Can be added for additional surge protection
C3, C4, C5, C6, C7, C8, C9, C10 Can be added for additional filtering control on the input pins
R1, R2, R3, R4, R5, R6, R7, R8 RTHR, Replace to modify voltage transition thresholds
R10, R11, R12, R13, R14, R15, R16, R17 RPAR, Replace according to RILIM selection
R18 RILIM, Replace to modify current limit drawn from each digital input