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  • TAS5721 Digital Audio Power Amplifier With EQ, DRC, 2.1 Support, and Headphone/Line Driver

    • SLOS739A July   2012  – March 2016 TAS5721

      PRODUCTION DATA.  

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  • TAS5721 Digital Audio Power Amplifier With EQ, DRC, 2.1 Support, and Headphone/Line Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - I/O Pin Characteristics
    6. 7.6  Master Clock Characteristics
    7. 7.7  Speaker Amplifier Characteristics
    8. 7.8  Headphone Amplifier and Line Driver Characteristics
    9. 7.9  Protection Characteristics
    10. 7.10 I2C Serial Control Port Requirements and Specifications
    11. 7.11 Serial Audio Port Timing
    12. 7.12 Typical Characteristics
      1. 7.12.1 Headphone Typical Characteristics
      2. 7.12.2 Line Driver Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power Supply
      2. 9.3.2  I2C Address Selection and Fault Output
      3. 9.3.3  Device Protection System
        1. 9.3.3.1 Overcurrent (OC) Protection With Current Limiting
        2. 9.3.3.2 Overtemperature Protection
        3. 9.3.3.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
      4. 9.3.4  Clock, Auto Detection, and PLL
      5. 9.3.5  PWM Section
      6. 9.3.6  SSTIMER Functionality
      7. 9.3.7  2.1-Mode Support
        1. 9.3.7.1 Supply Pumping and Polarity Inversion for 2.1 Mode
      8. 9.3.8  PBTL-Mode Support
      9. 9.3.9  I2C Serial Control Interface
        1. 9.3.9.1 Single- and Multiple-Byte Transfers
        2. 9.3.9.2 Single-Byte Write
        3. 9.3.9.3 Multiple-Byte Write
        4. 9.3.9.4 Single-Byte Read
        5. 9.3.9.5 Multiple-Byte Read
      10. 9.3.10 Dynamic Range Control (DRC)
      11. 9.3.11 Bank Switching
      12. 9.3.12 Serial Data Interface
        1. 9.3.12.1 Serial Interface Control and Timing
          1. 9.3.12.1.1 I2S Timing
          2. 9.3.12.1.2 Left-Justified
          3. 9.3.12.1.3 Right-Justified
      13. 9.3.13 DirectPath Headphone/Line Driver
        1. 9.3.13.1 Using Headphone Amplifier in TAS5721
        2. 9.3.13.2 Using Line Driver Amplifier in TAS5721
    4. 9.4 Device Functional Modes
      1. 9.4.1 Output Mode and MUX Selection
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
        1. 9.5.1.1 I2C Device Address Change Procedure
      2. 9.5.2 26-Bit 3.23 Number Format
    6. 9.6 Register Maps
      1. 9.6.1  Clock Control Register (0x00)
      2. 9.6.2  Device ID Register (0x01)
      3. 9.6.3  Error Status Register (0x02)
      4. 9.6.4  System Control Register 1 (0x03)
      5. 9.6.5  Serial Data Interface Register (0x04)
      6. 9.6.6  System Control Register 2 (0x05)
      7. 9.6.7  Soft Mute Register (0x06)
      8. 9.6.8  Volume Registers (0x07, 0x08, 0x09, 0x0A)
      9. 9.6.9  Volume Configuration Register (0x0E)
      10. 9.6.10 Modulation Limit Register (0x10)
      11. 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
      12. 9.6.12 Pwm Shutdown Group Register (0x19)
      13. 9.6.13 Start/stop Period Register (0x1A)
      14. 9.6.14 Oscillator Trim Register (0x1B)
      15. 9.6.15 BKND_ERR Register (0x1C)
      16. 9.6.16 Input Multiplexer Register (0x20)
      17. 9.6.17 Channel 4 Source Select Register (0x21)
      18. 9.6.18 PWM Output MUX Register (0x25)
      19. 9.6.19 DRC Control (0x46)
      20. 9.6.20 Bank Switch and EQ Control (0x50)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Component Selection and Hardware Connections
        2. 10.2.2.2 I2C Pullup Resistors
        3. 10.2.2.3 Digital I/O Connectivity
        4. 10.2.2.4 Recommended Startup and Shutdown Procedures
          1. 10.2.2.4.1 Recommended Use Model
            1. 10.2.2.4.1.1 Initialization Sequence
            2. 10.2.2.4.1.2 Normal Operation
            3. 10.2.2.4.1.3 Shutdown Sequence
            4. 10.2.2.4.1.4 Power-Down Sequence
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 DVDD and AVDD Supplies
    2. 11.2 PVDD Power Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE
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DATA SHEET

TAS5721 Digital Audio Power Amplifier With EQ, DRC, 2.1 Support, and Headphone/Line Driver

1 Features

  • Audio Input/Output
    • 10 W x 2 into 8 Ω With PVDD = 24 V
    • 8 W x 2 + 12 W x 1 into 8 Ω With PVDD = 24 V
    • Supports 2.0, Single Device 2.1, and Mono Modes
    • Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S)
    • Integrated DirectPath™ Headphone Amplifier and 2 VRMS Line Driver
  • Audio/PWM Processing
    • Independent Channel Volume Controls With 24-dB to Mute in 0.5 dB Steps
    • Separate Dynamic Range Control for Satellite and Sub Channels
    • 21 Programmable Biquads for Speaker EQ
    • Programmable Two-Band Dynamic Range Control
    • Support for 3D Effects
  • General Features
    • I2C™ Serial Control Interface Operational Without MCLK
    • Configurable I2C Address (0x34 or 0x36)
    • Automatic Sample Rate Detection
    • Thermal and Short-Circuit Protection
    • Wide PVDD Supply Range (4.5 V to 24 V)

2 Applications

    LED/LCD TVs, Soundbar, Docking Stations, PC Speakers

3 Description

The TAS5721 is an efficient, digital-input audio amplifier for driving 2.0 speaker systems configured as a bridge tied load (BTL), 2.1 systems with two satellite speakers and one subwoofer, or in PBTL systems driving a single speaker configured as a parallel bridge tied load (PBTL). One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data formats and sample rates. A fully programmable data path routes these channels to the internal speaker drivers.

The TAS5721 is a slave-only device, receiving all clocks from external sources. The TAS5721 operates with a PWM carrier frequency between a 384-kHz switching rate and a 288-KHz switching rate, depending on the input sample rate. Oversampling, combined with a fourth-order noise shaper, provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.

An integrated ground centered DirectPath™ combination headphone amplifier and 2VRMS line driver is integrated in the TAS5721.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS5721 HTSSOP (48) 12.50 mm × 6.10 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Output Power vs. PVDD in 2.0 Mode

TAS5721 C001_PVDDvPo8Vto24V4R6R8R.png

Signal Processing Flow

TAS5721 signal_processing_flow_slos739.gif

4 Revision History

Changes from * Revision (July 2012) to A Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

5 Device Comparison Table

TAS5721 TAS5731M TAS5729MD TAS5727
Max. Power to Single-Ended Load 10 18
Max. Power to Bridge Tied Load 15 37 20 35
Max. Power to Parallel Bridge Tied Load 30 70 40 70
Min. Supported Single-Ended Load 4 2
Min. Supported Bridge Tied Load 8 4 4 4
Min. Supported Parallel Bridge Tied Load 4 2 4 2
Closed/Open Loop Open Open Open Open
Max Speaker Outputs (#) 3 3 2 2
Headphone Channels Yes No Yes No
Architecture Class D Class D Class D Class D
Dynamic Range Control (DRC) 2-Band DRC 2-Band DRC 2-Band AGL 2-Band AGL
Biquads (EQ) 21 21 28 28

6 Pin Configuration and Functions

DCA Package
48-Pin HTSSOP
Top View
TAS5721 PO_DCA_TAS5721_SLOS739.gif

Pin Functions

PIN TYPE(1) TERMINATION DESCRIPTION
NAME NO.
ADR/FAULT 20 DI/DO - Dual function terminal which sets the LSB of the I2C address to 0 if pulled to GND, 1 if pulled to DVDD. If configured to be a fault output by the methods described in I²C Address Selection and Fault Output, this terminal is pulled low when an internal fault occurs. A pull-up or pull-down resistor is required, as is shown in the Typical Application Circuit Diagrams.
AGND 36 P - Ground reference for analog circuitry(3)
AVDD 19 P - Power supply for internal analog circuitry
AVDD_REG1 18 P - Voltage regulator derived from AVDD supply(2)
AVDD_REG2 37 P - Voltage regulator derived from AVDD supply(2)
BSTRPx 3, 42, 46, 47 P - Connection points for the bootstrap capacitors, which are used to create a power supply for the high-side gate drive of the device
DGND 35 P - Ground reference for digital circuitry(3)
DR_CN 12 P - Negative terminal for capacitor connection used in headphone amplifier and line driver charge pump
DR_CP 13 P - Positive terminal for capacitor connection used in headphone amplifier and line driver charge pump
DR_INx 7, 10 AI - Input for channel A or B of headphone amplifier or line driver
DR_OUTx 8, 9 AO - Output for channel A or B of headphone amplifier or line driver
DR_SD 39 DI - Places the headphone amplifier/line driver in shutdown when pulled low.
DR_VSS 11 P - Negative supply generated by charge pump for ground centered headphone and line driver output
DRVDD 14 P - Power supply for internal headphone and line driver circuitry
DVDD 34 P - Power supply for the internal digital circuitry
DVDD_REG 24 P - Voltage regulator derived from DVDD supply(2)
GVDD_REG 40 P - Voltage regulator derived from PVDD supply(2)
LRCLK 26 DI Pulldown Word select clock for the digital signal that is active on the input data line of the serial port
MCLK 21 DI Pulldown Master clock used for internal clock tree and sub-circuit and state machine clocking
NC 31 - - Not connected inside the device (all no connect terminals should be connected to ground)
OSC_GND 23 P - Ground reference for oscillator circuitry (this terminal should be connected to the system ground)
OSC_RES 22 AO - Connection point for oscillator trim resistor
PDN 25 DI Pullup Quick powerdown of the device that is used upon an unexpected loss of PVDD or DVDD power supply in order to quickly transition the outputs of the speaker amplifier to a 50/50 duty cycle. This quick powerdown feature avoids the audible anamolies that would occur as a result of loss of either of the supplies. If this pin is used to place the device into quick powerdown mode, the RST pin of the device must be toggled before the device is brought out of quick powerdown.
PGND 1 P - Ground reference for power device circuitry(3)
PLL_FLTM 16 AI/AO - Negative connection point for the PLL loop filter components
PLL_FLTP 17 AI/AO - Positive connection point for the PLL loop filter components
PLL_GND 15 P - Ground reference for PLL circuitry (this terminal should be connected to the system ground)
PowerPAD - P - Thermal and ground pad thatprovides both an electrical connection to the ground plane and a thermal path to the PCB for heat dissipation. This pad must be grounded to the system ground.
PVDD 4, 41 P - Power supply for internal power circuitry
RST 32 DI Pullup Places the device in reset when pulled low
SCL 30 DI - I2C serial control port clock
SCLK 27 DI Pulldown Bit clock for the digital signal that is active on the input data line of the serial data port
SDA 29 DI/DO - I2C serial control port data
SDIN 28 DI Pulldown Data line to the serial data port
SPK_OUTx 2, 43, 45, 48 AO - Speaker amplifier outputs
SSTIMER 38 AI - Connection point for the capacitor that is used by the ramp timing circuit, as described in Output Mode and MUX Selection
TEST1 5 DO - Used by TI for testing during device production (this terminal must be left floating)
TEST2 6 DO - Used by TI for testing during device production (this terminal must be left floating)
TEST3 33 DI - Used by TI for testing during device production (this terminal must be connected to GND)
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
(3) This terminal should be connected to the system ground

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted). (1)
MIN MAX UNIT
Supply voltage DVDD, AVDD, DRVDD –0.3 3.6 V
PVDD –0.3 30 V
DR_INx –0.3 DRVDD + 6 V
Input voltage 3.3-V digital input –0.5 DVDD + 0.5 V
5-V tolerant(2) digital input (except MCLK) –0.5 DVDD + 2.5(4)
5-V tolerant MCLK input –0.5 AVDD + 2.5(4)
SPK_OUTx to GND 32(3) V
BSTRPx to GND 39(3) V
Operating free-air temperature 0 85 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RST, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
(3) DC voltage + peak AC waveform measured at the pin should be below the allowed limit for all conditions.
(4) Maximum pin voltage should not exceed 6 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
xVDD Digital, analog, headphone supply voltage 3 3.3 3.6 V
PVDD Half-bridge supply voltage 8 26.4(1) V
VIH High-level input voltage 5-V tolerant 2 V
VIL Low-level input voltage 5-V tolerant 0.8 V
TA Operating ambient temperature 0 85 °C
TJ (2) Operating junction temperature 0 125 °C
RSPK
(SE, BTL, and PBTL)		 Minimum supported speaker impedance Output filter: L = 15 μH, C = 330 nF 4 8 Ω
Lo(BTL) Output-filter inductance Minimum output inductance
under short-circuit condition		 10 μH
RHP Headphone mode load impedance 16 32 Ω
RLD Line-diver mode load impedance 0.6 10 kΩ
(1) For operation at PVDD levels greater than 18 V, the modulation limit must be set to 93.8% via the control port register 0x10.
(2) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.

7.4 Thermal Information

THERMAL METRIC(1) TAS5721 UNIT
DCA (HTSSOP)
48 PINS
RθJA Junction-to-ambient thermal resistance 27.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 20.7 °C/W
RθJB Junction-to-board thermal resistance 13 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 6.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics – I/O Pin Characteristics

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage ADR/FAULT and SDA IOH = –4 mA
DVDD = AVDD = 3 V		 2.4 V
VOL Low-level output voltage IOL = 4 mA
DVDD = AVDD = 3 V		 0.5
IIL Low-level input current Digital Inputs VI < VIL ; DVDD = AVDD = 3.6 V
 75 μA
IIH High-level input current VI > VIH ; DVDD = AVDD = 3.6 V
 75
IDD 3.3 V supply current 3.3 V supply voltage (DVDD, AVDD) Normal mode 48 70 mA
Reset (RST = low, PDN = high, DR_SD = low) 21 38
tw(RST) Pulse duration, RST active RST 100 μs
td(I2C_ready) Time before the I2C port is able communicate after RST goes high 12 ms

7.6 Master Clock Characteristics(1)

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLK MCLK frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
tr(MCLK) / tf(MCLK) Rise/fall time for MCLK 5 ns
(1) For clocks related to the serial audio port, please see Serial Audio Port Timing

7.7 Speaker Amplifier Characteristics

TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PoSPK (BTL) Power output per channel of speaker amplifier when used in BTL mode (2) PVDD = 18 V, RSPK = 8Ω, 1-kHz input signal 10 W
PVDD = 12 V, RSPK = 8Ω, 10% THD+N, 1-kHz input signal 8.8
PVDD = 12 V, RSPK = 8Ω, 7% THD+N, 1-kHz input signal 8.3
PVDD = 8 V, RSPK = 8Ω, 10% THD+N, 1-kHz input signal 4
PVDD = 8 V, RSPK = 8Ω, 7% THD+N, 1-kHz input signal 3.8
PoSPK (PBTL) Power output per channel of speaker amplifier when used in PBTL mode (2) PVDD = 12 V, RSPK = 4Ω,
10% THD+N, 1-kHz input signal		 10 W
PVDD = 12 V, RSPK = 4Ω,
7% THD+N, 1-kHz input signal		 10
PVDD = 18 V, RSPK = 4Ω,
1-kHz input signal		 10
PoSPK (SE) Power output per channel of speaker amplifier when used in SE mode (2) PVDD = 12 V, RSPK = 4 Ω,
10% THD+N, 1-kHz input signal		 4.3 W
PVDD = 24 V, RSPK = 4 Ω,
10% THD+N, 1-kHz input signal		 5.5
THD+N Total harmonic distortion + noise PVDD = 18 V, PO = 1 W 0.07%
PVDD = 12 V, PO = 1 W 0.11%
PVDD = 8 V, PO = 1 W 0.2%
ICN Idle channel noise A-weighted 61 μV
Crosstalk PO = 1 W, f = 1 kHz (BD Mode), PVDD = 24 V 58 dB
PO =1 W, f = 1 kHz (AD Mode), PVDD = 24 V 48 dB
SNR Signal-to-noise ratio(1) A-weighted, f = 1 kHz, maximum power at THD < 1% 106 dB
fPWM Output switching frequency 11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz
48/24/12/8/16/32-kHz data rate ±2% 384
IPVDD Supply current No load (PVDD) Normal mode 32 50 mA
Reset (RST = low, PDN = high) 5 8
rDS(on) Drain-to-source resistance (for each of the Low-Side and High-Side Devices) TJ = 25°C, includes metallization resistance 200 mΩ
RPD Internal pulldown resistor at the output of each half-bridge Connected when drivers are in the high-impedance state to provide bootstrap capacitor charge. 3 kΩ
(1) SNR is calculated relative to 0-dBFS input level.
(2) Power levels are thermally limited.

7.8 Headphone Amplifier and Line Driver Characteristics

TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PoHP Power output per channel of headphone amplifier DRVDD = 3.3 V (RHP = 32; THD = 1%) 50 mW
AVDR Gain for headphone amplifier and line driver Adjustable through Rin and Rfb - dB
SNRHP Signal-to-noise ratio (headphone mode) Rhp = 32 101 dB
SNRLD Signal-to-noise ratio (line driver mode) 2-VRMS output 105 dB

7.9 Protection Characteristics

TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
MIN TYP MAX UNIT
Vuvp(fall) Undervoltage protection limit PVDD falling 4 V
Vuvp(rise) Undervoltage protection limit PVDD rising 4.1 V
OTE Overtemperature error threshold 150 °C
ΔOTE Variation in overtemperature detection circuit ±15 °C
IOCE Overcurrent limit protection threshold 3 A
tOCE Overcurrent response time 150 ns

7.10 I2C Serial Control Port Requirements and Specifications

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
MIN MAX UNIT
fSCL Frequency, SCL No wait states 400 kHz
tw(H) Pulse duration, SCL high 0.6 μs
tw(L) Pulse duration, SCL low 1.3 μs
tr Rise time, SCL and SDA 300 ns
tf Fall time, SCL and SDA 300 ns
tsu1 Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 0 ns
t(buf) Bus free time between stop and start conditions 1.3 μs
tsu2 Setup time, SCL to start condition 0.6 μs
th2 Hold time, start condition to SCL 0.6 μs
tsu3 Setup time, SCL to stop condition 0.6 μs
CL Load capacitance for each bus line 400 pF

7.11 Serial Audio Port Timing

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified).
MIN TYP MAX UNIT
fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL = 30 pF 1.024 12.288 MHz
tsu1 Setup time, LRCLK to SCLK rising edge 10 ns
th1 Hold time, LRCLK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK rising edges between LRCLK rising edges 32 64 SCLK edges
t(edge) LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4 SCLK period
tr/tf Rise/fall time for SCLK/LRCLK 8 ns
LRCLK allowable drift before LRCLK reset 4 MCLK Periods
TAS5721 sys_init_tas5733.gif

NOTE:

On power up, it is recommended that the TAS5721 RST be held LOW for at least 100 μs after DVDD has reached 3 V.

NOTE:

If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH).
Figure 1. Reset Timing
TAS5721 t0027-01.gif Figure 2. SCL and SDA Timing
TAS5721 t0028-01.gif Figure 3. Start and Stop Conditions Timing
TAS5721 t0026-04_los556.gif Figure 4. Serial Audio Port Timing

7.12 Typical Characteristics

TAS5721 C002_SEPVDDvPo8Vto24V4R8R.png Figure 5. Output Power vs PVDD IN 2.1 Mode
TAS5721 G004_THDvFreq12V4R6R8R.png Figure 7. Total Harmonic Distortion + Noise vs Frequency in 2.0 Mode With PVDD = 12 V
TAS5721 G006_THDvFreq24V4R6R8R.png Figure 9. Total Harmonic Distortion + Noise vs Frequency in 2.0 Mode With PVDD = 24 V
TAS5721 G008_SETHDvFreq18V4R8R.png Figure 11. Total Harmonic Distortion + Noise vs Frequency in 2.1 Mode With PVDD = 18 V
TAS5721 G010_PBTLTHDvFreq12V4R6R8R.png Figure 13. Total Harmonic Distortion + Noise vs Frequency in PBTL Mode With PVDD = 12 V
TAS5721 G012_PBTLTHDvFreq24V4R6R8R.png Figure 15. Total Harmonic Distortion + Noise vs Frequency in PBTL Mode With PVDD = 24 V
TAS5721 G014_SEPVDDvICN8Vto24V4R8R.png Figure 17. 2.1 Idle Channel Noise vs PVDD
TAS5721 C016_THDvPo1kHz12V4R6R8R.png Figure 19. Total Harmonic Distortion + Noise vs Output Power in 2.0 Mode With PVDD = 12 V
TAS5721 C018_THDvPo1kHz24V4R6R8R.png Figure 21. Total Harmonic Distortion + Noise vs Output Power in 2.0 Mode With PVDD = 24 V
TAS5721 C020_SETHDvPo1kHz18V4R8R.png Figure 23. Total Harmonic Distortion + Noise vs Output Power in 2.1 Mode With PVDD = 18 V
TAS5721 C022_PBTLTHDvPo1kHz12V2R4R.png Figure 25. Total Harmonic Distortion + Noise vs Output Power in PBTL Mode With PVDD = 12 V
TAS5721 C024_PBTLTHDvPo1kHz24V2R4R.png Figure 27. Total Harmonic Distortion + Noise vs Output Power in PBTL Mode With PVDD = 24 V
TAS5721 G026_EffvPo12V18V24V8R8R8R.png
All channels driven
Figure 29. Efficiency vs Output Power in 2.1 Mode
TAS5721 G029_PBTLEffvPo12V18V24V8R.png
All channels driven
Figure 31. Efficiency vs Output Power in PBTL Mode
TAS5721 G032_XtalkvFreq12V4R.png Figure 33. Crosstalk vs Frequency in 2.0 Mode
TAS5721 G034_XtalkvFreq24V4R.png Figure 35. Crosstalk vs Frequency in 2.0 Mode
TAS5721 G036_SEXtalkvFreq12V8R.png Figure 37. Crosstalk vs Frequency in 2.1 Mode
TAS5721 G038_SEXtalkvFreq24V8R.png Figure 39. Crosstalk vs Frequency in 2.1 Mode
TAS5721 C003_PBTLPVDDvPo8Vto24V4R6R8R.png Figure 6. Output Power vs PVDD in PBTL Mode
TAS5721 G005_THDvFreq18V4R6R8R.png Figure 8. Total Harmonic Distortion + Noise vs Frequency in 2.0 Mode With PVDD = 18 V
TAS5721 G007_SETHDvFreq12V4R8R.png Figure 10. Total Harmonic Distortion + Noise vs Frequency in 2.1 Mode With PVDD = 12 V
TAS5721 G009_SETHDvFreq24V4R8R.png Figure 12. Total Harmonic Distortion + Noise vs Frequency in 2.1 Mode With PVDD = 24 V
TAS5721 G011_PBTLTHDvFreq18V4R6R8R.png Figure 14. Total Harmonic Distortion + Noise vs Frequency in PBTL Mode With PVDD = 18 V
TAS5721 G013_PVDDvICN8Vto24V4R6R8R.png Figure 16. 2.0 Idle Channel Noise vs PVDD
TAS5721 G015_PVDDvICN8Vto24V4R6R8R.png Figure 18. PBTL Idle Channel Noise vs PVDD
TAS5721 C017_THDvPo1kHz18V4R6R8R.png Figure 20. Total Harmonic Distortion + Noise vs Output Power in 2.0 Mode With PVDD = 18 V
TAS5721 C019_SETHDvPo1kHz12V4R8R.png Figure 22. Total Harmonic Distortion + Noise vs Output Power in 2.1 Mode With PVDD = 12 V
TAS5721 C021_SETHDvPo1kHz24V4R8R.png Figure 24. Total Harmonic Distortion + Noise vs Output Power in 2.1 Mode With PVDD = 24 V
TAS5721 C023_PBTLTHDvPo1kHz18V2R4R.png Figure 26. Total Harmonic Distortion + Noise vs Output Power in PBTL Mode With PVDD = 18 V
TAS5721 G025_EffvPo12V18V24V8R.png
All channels driven
Figure 28. Efficiency vs Output Power in 2.0 Mode
TAS5721 G027_EffvPo12V18V24V4R4R8R.png
All channels driven
Figure 30. Efficiency vs Output Power in 2.1 Mode
TAS5721 G030_PBTLEffvPo12V18V24V6R.png
All channels driven
Figure 32. Efficiency vs Output Power in PBTL Mode
TAS5721 G033_XtalkvFreq12V8R.png Figure 34. Crosstalk vs Frequency in 2.0 Mode
TAS5721 G035_XtalkvFreq24V8R.png Figure 36. Crosstalk vs Frequency in 2.0 Mode
TAS5721 G037_SEXtalkvFreq12V4R.png Figure 38. Crosstalk vs Frequency in 2.1 Mode
TAS5721 G039_SEXtalkvFreq24V4R.png Figure 40. Crosstalk vs Frequency in 2.1 Mode

7.12.1 Headphone Typical Characteristics

TAS5721 G040_HPTHDvFreq3p3V16R32R.png Figure 41. Total Harmonic Distortion + Noise vs Frequency Headphone With DRVDD = 3.3 V
TAS5721 G042_HPTHDvPo1kHz3p3V16R32R.png Figure 43. Total Harmonic Distortion + Noise vs Output Power Headphone With DRVDD = 3.3 V
TAS5721 G041_HPTHDvFreq3p3V5kR10kR.png Figure 42. Total Harmonic Distortion + Noise vs Frequency Headphone With DRVDD = 3.3 V

7.12.2 Line Driver Typical Characteristics

TAS5721 G043_HPTHDvVo1kHz3p3V5kR10kR.png Figure 44. Total Harmonic Distortion + Noise vs Output Voltage Headphone With DRVDD = 3.3 V
TAS5721 G045_HPXtalkvFreq3p3V16R.png Figure 46. Crosstalk vs Frequency Headphone With DRVDD = 3.3 V
TAS5721 G044_HPXtalkvFreq3p3V5kR.png Figure 45. Crosstalk vs Frequency Headphone With DRVDD = 3.3 V
TAS5721 G046_HPXtalkvFreq3p3V32R.png Figure 47. Crosstalk vs Frequency Headphone With DRVDD = 3.3 V

 
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