SLOS821B June   2013  – September 2014 TPA6133A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Application Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Headphone Amplifiers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-Blocking Capacitors
        2. 9.2.2.2 Charge Pump Flying Capacitor and CPVSS Capacitor
        3. 9.2.2.3 Decoupling Capacitors
        4. 9.2.2.4 Optional Test Setup
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelimes
      1. 11.1.1 Exposed Pad On TPA6133A2RTJ Package
      2. 11.1.2 GND Connections
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7 Specification

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range, TA = 25°C (unless otherwise noted)
MIN MAX UNIT
Supply voltage, VDD –0.3 6 V
Input voltage RIGHTINx, LEFTINx CPVSS-0.2 V to minimum of
(3.6 V, VDD+0.2 V)
SD, TEST1, TEST2 –0.3 7 V
Output continuous total power dissipation See the Thermal Information Table
Operating free-air temperature range, TA –40 85 °C
Operating junction temperature range, TJ –40 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –3 3 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –750 750 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
Supply voltage, VDD 2.5 5.5 V
VIH High-level input voltage TEST1, TEST2, SD 1.3 V
VIL Low-level input voltage SD 0.35 V
Minimum Load Impedance 12.8 Ω
TA Operating free-air temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1) RTJ UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 34.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.5
RθJB Junction-to-board thermal resistance 11.6
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 11.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOS| Output offset voltage VDD = 2.5 V to 5.5 V, inputs grounded 135 400 μV
PSRR DC Power supply rejection ratio VDD = 2.5 V to 5.5 V, inputs grounded –101 -85 dB
CMRR Common mode rejection ratio VDD = 2.5 V to 5.5 V –69 dB
|IIH| High-level input current VDD = 5.5 V, VI = VDD TEST1, TEST2 1 µA
SD 10
|IIL| Low-level input current VDD = 5.5 V, VI = 0 V SD 1 µA
IDD Supply current VDD = 2.5 V to 5.5 V, SD = VDD 4.2 6 mA
Shutdown mode, VDD = 2.5V to 5.5 V, SD = 0 V 0.08 1 µA

7.6 Operating Characteristics

VDD = 3.6 V , TA = 25°C, RL = 16 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power Stereo, Outputs out of phase,
THD = 1%, f = 1 kHz, Gain = +4 dB		 VDD = 2.5V 63 mW
VDD = 3.6V 133
VDD = 5V 142
THD+N Total harmonic distortion plus noise PO = 35 mW f = 100 Hz 0.0096%
f = 1 kHz 0.007%
f = 20 kHz 0.0021%
kSVR Supply ripple rejection ratio 200 mVpp ripple, f = 217 Hz -94.3 -85 dB
200 mVpp ripple, f = 1 kHz -92
200 mVpp ripple, f = 20 kHz -77.1
Av Channel DC Gain SD = VDD 1.597 V/V
ΔAv Gain matching 0.1%
Slew rate 0.4 V/µs
Vn Noise output voltage VDD = 3.6V, A-weighted, Gain = +4 dB 12 µVRMS
fosc Charge pump switching frequency 300 381 500 kHz
Start-up time from shutdown 4.8 ms
Differential input impedance 36.6 kΩ
SNR Signal-to-noise ratio Po = 35 mW 93 dB
Thermal shutdown Threshold 180 °C
Hysteresis 35 °C
ZO HW Shutdown HP output impedance SD = 0 V, measured output to ground. 112 Ω
CO Output capacitance 80 pF

7.7 Typical Characteristics

Table 1. Table of Graphs

Figure
Total harmonic distortion + noise versus Output power Figure 1–Figure 4
Total harmonic distortion + noise versus Frequency Figure 5–Figure 12
Supply voltage rejection ratio versus Frequency Figure 13-Figure 14
Common mode rejection ratio versus Frequency Figure 15-Figure 16
Crosstalk versus Frequency Figure 17-Figure 18
C(PUMP, DECOUPLE, ,BYPASS, CPVSS) = 1 μF, CI = 2.2 µF. All THD + N graphs taken with outputs out of phase (unless otherwise noted).
C001_THDvPo1kHz3p6V16RPhase.pngFigure 1. Total Harmonic Distortion + Noise vs Output Power
C003_THDvPo1kHz16R.pngFigure 3. Total Harmonic Distortion + Noise vs Output Power
C002_THDvPo1kHz3p6V32RPhase.pngFigure 2. Total Harmonic Distortion + Noise vs Output Power
C004_THDvPo1kHz32R.pngFigure 4. Total Harmonic Distortion + Noise vs Output Power
C005_THDvFreq2p5V16R.pngFigure 5. Total Harmonic Distortion + Noise vs Frequency
C007_THDvFreq3p6V16R.pngFigure 7. Total Harmonic Distortion + Noise vs Frequency
C009_THDvFreq2p5V32R.pngFigure 9. Total Harmonic Distortion + Noise vs Frequency
C011_THDvFreq3p6V32R.pngFigure 11. Total Harmonic Distortion + Noise vs Frequency
C013_PSRRvFreq16R.pngFigure 13. Supply Voltage Rejection Ratio vs Frequency
C015_CMRRvFreq16R.pngFigure 15. Common Mode Rejection Ratio vs Frequency
C017_XtalkvFreq16R.pngFigure 17. Crosstalk vs Frequency
C006_THDvFreq3V16R.pngFigure 6. Total Harmonic Distortion + Noise vs Frequency
C008_THDvFreq5V16R.pngFigure 8. Total Harmonic Distortion + Noise vs Frequency
C010_THDvFreq3V32R.pngFigure 10. Total Harmonic Distortion + Noise vs Frequency
C012_THDvFreq5V32R.pngFigure 12. Total Harmonic Distortion + Noise vs Frequency
C014_PSRRvFreq32R.pngFigure 14. Supply Voltage Rejection Ratio vs Frequency
C016_CMRRvFreq32R.pngFigure 16. Common Mode Rejection Ratio vs Frequency
C018_XtalkvFreq32R.pngFigure 18. Crosstalk vs Frequency