SLPA018 October 2021 JFE150
The JFET pre-amp circuit is easiest to analyze using the small-signal T-model as shown in Figure 2-1. To understand the operation of this circuit, begin by examining it at the input. A sensor generates a small-signal input voltage (vin), which modulates the gate-to-source voltage (vgs) of the JFET. The JFE150 is the first gain stage in the pre-amp circuit and conducts a small-signal drain-to-source current, ids = gm × vgs which fluctuates with vin. The small signal current ids, is not to be confused with the DC bias current, IDS = 2 mA, as shown in Figure 1-1. The transconductance gain parameter (gm), is expressed in Siemens and vgs is expressed in volts.
Combined with resistor R1, the OPA202 forms a transimpedance amplifier that converts the current gm × vgs to a voltage, vout. The OPA202 drives the loop to keep its input terminals approximately equal. As a result, most of the current gm × vgs flows through resistor R1 in the mid-band frequencies, producing an amplified voltage at vout. Equation 1 calculates the feedforward gain (Av):
Convert gm from decibels to Siemens (mA/V) or Ω–1, as shown in Equation 2, using the simulated measurement from Figure 2-2.
Equation 3 and Equation 4 show that the feedforward gain is:
Because wafer process variations can yield up to 30% variations in gm, adding a feedback network (β) maintains a predictable closed-loop gain. The β feedback network consists of resistors RF2, RS1, and RS2 and capacitor CS, and is a series-shunt feedback network. The β network samples vout by shunting the output of the OPA202 and feeds back a proportional voltage vfb in series with vgs. The source node of the JFET is the feedback-summing node of the circuit. In this configuration, the loop is closed. If vout rises, then vfb rises. An increase of vfb at the source node decreases vgs, resulting in a reduction of current gm × vgs that flows through transimpedance resistor R1. The final outcome is a reduction of vout which completes the negative feedback loop of the pre-amplifier. The standard closed-loop gain (Acl) Equation 5 applies.
Assuming the feed forward gain A is much greater than β, Acl is approximately determined by resistors RF2 and RS2 in the mid-band frequencies. At frequency, CS becomes a short and Acl can be approximately calculated using Equation 6.
Figure 2-3 shows the closed-loop gain vs frequency response of the JFET pre-amplifier circuit.
The loop parameters A, and 1/β can be determined in simulation by breaking the loop. This is accomplished in a SPICE simulator by driving the loop with VLoop as shown in Figure 2-4.
At high frequencies the inductor L1 is an open and the capacitor C2 is a short. This method isolates the circuits A and β, to plot the frequency response of each, as shown in Figure 2-5. The simulated feedforward gain A is 83.6 dB and closely matches the calculation from Equation 4. The upper –3 dB point of Acl occurs when A and 1/β meet.
The low-frequency corners are straightforward to determine and are shown in Figure 2-5, Figure 2-3, and Table 2-1. Frequency determines the transfer function between vin and the gate. Components RG and CG form a high-pass filter and the –3 dB point of this transfer function occurs at 15.9 mHz.
RC Combinations | Corner Frequencies |
---|---|
15.9 mHz | |
568.4 mHz | |
3.98 Hz (See curve A in Figure 2-5) | |
15.92 Hz |
Breaking the loop also allows the designer to check for circuit stability as shown with the loop gain (A × β) phase plot in Figure 2-6. The phase margin of this circuit is determined by starting the analysis when the phase of A × β is –180°. Figure 2-6 show that this occurs at The reason for starting at –180° is because CD does not contribute to the phase margin. Capacitor CD adds a 90° shift from the starting point of the analysis and is a high-pass filter zero. This can be seen in simulation by varying the value of CD from 10 µF to 5 F or through tedious hand calculations. The phase margin = 267.4 – 180 = 87.4°.