SLPU009 February   2022 JFE150

 

  1.   Trademarks
  2. 1Overview
    1. 1.1 JFE150
    2. 1.2 JFE150EVM
    3. 1.3 Related Documentation
    4. 1.4 Evaluation Module Limitations and Cautions
    5. 1.5 Electrostatic Discharge Caution
  3. 2Getting Started
    1. 2.1 Power Supplies
    2. 2.2 Input
    3. 2.3 Vbias
    4. 2.4 Output
    5. 2.5 Capacitors
  4. 3Application Circuit
    1. 3.1 JFE150 Ultra-Low-Noise Pre-Amp
  5. 4Schematic, PCB Layout, and Bill of Materials
    1. 4.1 JFE150EVM Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials

2.2 Input

The input to the JFE150EVM is designed to interface high-impedance sources to the gate of the JFET. The input is ac-coupled with capacitor C8 and the dc gate bias voltage is set with resistor R10. A single BNC connector and Vin test point are available at the input to allow for an easy interface with signal generators or other equipment. The midband gain of the circuit is approximately 1000 V/V or 60 dB, as shown in Figure 3-2. For example, a 1-mVpp, 1-kHz input signal produces an approximately 1-Vpp, 1-kHz signal measured on the output. The Design tools and simulation tab on the device web folder can assist with other configurations.