SLUAAQ5 May 2024 BQ769142 , BQ76942 , BQ76952 , BQ76972
There are two general methods for reducing gate turn-off times.
The first is shown in Figure 2-1 and offers a low cost design to speed up the turn-off by using a diode (D4) to provide a lower resistance path for the gate of the FET to discharge the stored charge compared to the turn on path. By varying the resistance, the time to turn-off can be increased or decreased as desired.
The second is shown in Figure 2-2. This circuit uses the ability to drive the PMOS low quicker to provide an alternate path for the charge of the FETs to drain from the gate and into PACK+. This configuration, while more expensive, is an excellent choice for situations where multiple FETs are in parallel due to the ability to get a lower resistance. If the user is using only one or two FETs, option one is more cost efficient.