SLUUC74 May 2021 BQ25720 , BQ25723
The BQ2572x evaluation modules are complete charger modules for evaluating an SMBus or I2C-controlled buck boost charger using the BQ2572x devices.
The BQ2572x EVM does not include the EV2400 interface board. To evaluate the BQ2572x EVM, order an EV2400 interface board separately.
The BQ2572x is a synchronous NVDC-1 battery buck boost charge controller, offering a low component count, high efficiency solution for space-constrained, multi-chemistry battery charging applications.
The NVDC-1 configuration allows the system to be regulated at the battery voltage, but does not drop below the system minimum voltage. The system keeps operating even when the battery is completely discharged or removed. When load power exceeds the input source rating, the battery supplement mode prevents the input source from being overloaded.
The BQ2572x charges the battery from a wide range of input sources including a 5-V USB adapter to a high-voltage USB PD source and traditional adapters.
During power up, the charger sets the converter to buck, boost, or buck-boost configuration based on the input source and battery conditions. During the charging cycle, the charger automatically transits among buck, boost, and buck-boost configuration without host control.
The BQ2572x monitors adapter current, battery current, and system power. The flexibly programmed PROCHOT output goes directly to the CPU for throttle back, when needed.
For more details on register functions, see the BQ25720 SMBus 1- to 4-Cell Narrow VDC Buck-Boost Battery Charge Controller With System Power Monitor and Processor Hot Monitor and BQ25723 I2C 1- to 4-Cell Narrow VDC Buck-Boost Battery Charge Controller With System Power Monitor and Processor Hot Monitor data sheets.
Table 1-1 lists the I/O descriptions.
Jack | Description |
---|---|
J1–VIN | Input: positive terminal |
J1–PGND | Input: negative terminal (ground terminal) |
J2-ILIM_HIZ | External converter disable |
J2-CHRG_OK | CHRG_OK output |
J2-ENZ_OTG | External OTG disable pin |
J2-CELL_control | External battery removal control; logic high to pull the CELL pin down |
J3–3V3 | Onboard 3.3-V output |
J3–SDA | SMBUS or I2C SDA |
J3-SCL | SMBUS or I2C SCL |
J3-GND | Ground |
J4-CMPOUT | CMPOUT pin output |
J4-GND | Ground |
J4-CMPIN | External CMPIN pin input |
J5-VBAT | Connected to battery pack output |
J5-PGND | Ground |
J6-VSYS | Connected to system output |
J6-PGND | Ground |
J7–SDA |
SMBUS or I2C SDA |
J7-SCL | SMBUS or I2C SCL |
J7-GND | Ground |
Table 1-2 displays the controls and key parameters settings.
Jumper | Description | Factory Setting |
---|---|---|
JP1 | Bypass inrush control circuit JP1 on: bypasses input FETs Q6 and Q7 external selector JP1 off: CHRG_OK controls Q6 and Q7 external selector |
Installed |
JP2 | Jumper on: Forward Mode Jumper off: OTG Mode |
Installed |
JP3 | CELL setting: 1S: JP3(1-2), measure CELL pin voltage 1.5 V 2S: JP3(3-4), measure CELL pin voltage 2.4 V 3S: JP3(5-6), measure CELL pin voltage 3.3 V 4S: JP3(7-8), measure CELL pin voltage 4.5 V |
2S setting: JP3(3-4) |
JP4 | Jumper on: Bat removal Jumper off: Cell setting by JP3 | Not installed |
JP6 | For input current setting: Jumper on: ILIM_HIZ LOW. Jumper off: Allow pre-bias ILIM_HIZ |
Not installed |
JP7 | VBUS source selection JP7 (1-2): VBUS pin on VIN JP7 (2-3): VBUS pin on ACP |
Installed: JP7(1-2) |
JP8 | Jumper on: Onboard LDO to drive the EVM 3V3 Jumper off: disconnect onboard LDO to drive the EVM 3V3 |
Installed |
Table 1-3 lists the recommended operating conditions.
Symbol | Description | MIN | TYP | MAX | Unit |
---|---|---|---|---|---|
Supply voltage, VIN | Input voltage from AC adapter input | 3.5 | 5, 9, 15, 20 | 26 | V |
Battery voltage, VBAT | Voltage applied at VBAT terminal | 0 | 19.2 | V | |
Supply current, IAC | Maximum input current from AC adapter input | 0 | 6.4 | A | |
Output current, Iout | Output current | 0 | 8 | A | |
Operating junction temperature range, TJ | 0 | 125 | °C |