The board layout for the TPSM843B22EVM is shown in Figure 4-1 through Figure 4-8. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper. The U1 circuit takes up an area of only approximately 605 mm² as shown on the silkscreen.

All of the required components for the TPSM843B22 are placed on the top layer for U1. The input and output capacitors are placed on the top layer in a symmetrical pattern. Additionally, the voltage set point is interchangable with J6 on the top layer. The top resistor is connected close to the module on the top layer, the interchangable bottom resistors are located on the bottom later. Additional three input bulk capacitors are used near the input terminal to limit the noise entering the module from the supply used to power the board. Critical analog circuits such as the EN resistors, MSEL resistors, and SYNC/FSEL resistors are kept close to the IC and terminated to the quiet analog ground (AGND).

The top layer contains the main power traces for VIN, VOUT and a short trace to measure SW. The top layer power traces are connected to the planes on other layers of the board with multiple vias placed around the board. There are multiple vias near the PGND pins of the module to help maximize the thermal performance. The TPSM843B22 circuit has its own dedicated ground for quiet analog ground that is connected to the main power ground plane at a single point. This single point connection is done on the internal ground planes on signal layer 1.

The mid layers 1 to 4 are mostly power ground planes with some traces. Some layers contain VIN copper area beneath the IC to connect VIN pins together with a low impedance connection.

The bottom layer is mostly a ground plane. This layer has additional VOUT copper area for the U1 circuit. In addition, this layer also contains the interchangable resistors for SYNC/FSEL, MSEL and EN pins along with more space to add extra output capacitors. EN resistors were left unpopulated to allow the user to add accordingly to desired startup. In addition, BP5 resistor, Feedforward capacitor and resitor, 50-ohm resistor for bode measurements and 50-ohm resistor for VOUT SMB connection can be found on this layer.

Figure 4-1 Top-Side Composite View

Figure 4-3 Top Layer Layout

Figure 4-5 Mid Layer 2 Layout

Figure 4-7 Mid Layer 4 Layout

Figure 4-2 Bottom-Side Composite View (Viewed From Bottom)

Figure 4-4 Mid Layer 1 Layout

Figure 4-6 Mid Layer 3 Layout

Figure 4-8 Bottom Layer Layout