SLVA275C january   2010  – may 2023 UCD9081

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware
    1. 2.1 Package: RHB (S-PQFP-N32), 32-Pin Plastic Quad Flatpack
    2. 2.2 Hardware and Pinout
    3. 2.3 Detailed Pin Descriptions
      1. 2.3.1 RST
      2. 2.3.2 SDA
      3. 2.3.3 SCL
      4. 2.3.4 ADDRx
      5. 2.3.5 ROSC
  5. 3Software
    1. 3.1 Data File Format
    2. 3.2 I2C Transactions
    3. 3.3 Device Version
    4. 3.4 Checksum
    5. 3.5 Sample Configuration Data File
      1. 3.5.1 Factory Default
      2. 3.5.2 EVM Default Configuration
    6. 3.6 I2C Write and Read Transaction Formats
      1. 3.6.1 I2C Write Transaction
      2. 3.6.2 I2C Read Transaction
    7. 3.7 Pseudo I2C Write and Read Transactions
      1. 3.7.1 UCD9081 I2C Transactions for Writing User Data and PARAMS
      2. 3.7.2 UCD9081 I2C Transactions for Reading User Data and PARAMS
  6. 4User Configuration
    1. 4.1 Configuration Parameter Memory Map
    2. 4.2 Configuration Parameter Detail
      1. 4.2.1  GpDir
      2. 4.2.2  NegateEnablePolarity
      3. 4.2.3  SeqEventPending
      4. 4.2.4  SequenceEventParameters
      5. 4.2.5  SequenceEventLink
      6. 4.2.6  SequenceEventData
      7. 4.2.7  DependencyMasks
      8. 4.2.8  UnderVoltageThresholds
      9. 4.2.9  OverVoltageThresholds
      10. 4.2.10 RampTime
      11. 4.2.11 OutOfRegulationWidth
      12. 4.2.12 UnsequenceTime
      13. 4.2.13 EnablePolarity
      14. 4.2.14 SaveRailLog
      15. 4.2.15 ReferenceSelect
      16. 4.2.16 LastUnusedSeq
      17. 4.2.17 IgnoreGlitchAlarms
      18. 4.2.18 IgnoreFlashErrorLog
      19. 4.2.19 Checksum
  7. 5Additional Considerations
    1. 5.1 Embedded Application
    2. 5.2 Timing
      1. 5.2.1 UCD9081 Startup
      2. 5.2.2 Clock Stretching After Flash Erase
      3. 5.2.3 Bit Timeout
      4. 5.2.4 Byte or Transaction Timeout
  8. 6References
  9. 7Revision History

SequenceEventLink

The SequenceEventLink field allows a parent rail (monitored input) to be specified for each ENx and GPOx output. The RESEQ bit (sequence after shutdown) allows an enable or GPO to be marked to sequence the system (as defined by the current sequencer configuration) after it has been shut down. The address map for these registers is as follows:

AddressSizeDefault ValueDescription
0xE08C10x01Rail 1 parent rail identifier and resequence indicator
0xE08D10x00Rail 2 parent rail identifier and resequence indicator
0xE08E10x01Rail 3 parent rail identifier and resequence indicator
0xE08F10x04Rail 4 parent rail identifier and resequence indicator
0xE09010x01Rail 5 parent rail identifier and resequence indicator
0xE09110x04Rail 6 parent rail identifier and resequence indicator
0xE09210x05Rail 7 parent rail identifier and resequence indicator
0xE09310x06Rail 8 parent rail identifier and resequence indicator
0xE09410x00GPO1 parent rail identifier and resequence indicator
0xE09510x00GPO2 parent rail identifier and resequence indicator
0xE09610x00GPO3 parent rail identifier and resequence indicator
0xE09710x00GPO4 parent rail identifier and resequence indicator

The format of each register is as follows:

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