SLVA275C january   2010  – may 2023 UCD9081

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware
    1. 2.1 Package: RHB (S-PQFP-N32), 32-Pin Plastic Quad Flatpack
    2. 2.2 Hardware and Pinout
    3. 2.3 Detailed Pin Descriptions
      1. 2.3.1 RST
      2. 2.3.2 SDA
      3. 2.3.3 SCL
      4. 2.3.4 ADDRx
      5. 2.3.5 ROSC
  5. 3Software
    1. 3.1 Data File Format
    2. 3.2 I2C Transactions
    3. 3.3 Device Version
    4. 3.4 Checksum
    5. 3.5 Sample Configuration Data File
      1. 3.5.1 Factory Default
      2. 3.5.2 EVM Default Configuration
    6. 3.6 I2C Write and Read Transaction Formats
      1. 3.6.1 I2C Write Transaction
      2. 3.6.2 I2C Read Transaction
    7. 3.7 Pseudo I2C Write and Read Transactions
      1. 3.7.1 UCD9081 I2C Transactions for Writing User Data and PARAMS
      2. 3.7.2 UCD9081 I2C Transactions for Reading User Data and PARAMS
  6. 4User Configuration
    1. 4.1 Configuration Parameter Memory Map
    2. 4.2 Configuration Parameter Detail
      1. 4.2.1  GpDir
      2. 4.2.2  NegateEnablePolarity
      3. 4.2.3  SeqEventPending
      4. 4.2.4  SequenceEventParameters
      5. 4.2.5  SequenceEventLink
      6. 4.2.6  SequenceEventData
      7. 4.2.7  DependencyMasks
      8. 4.2.8  UnderVoltageThresholds
      9. 4.2.9  OverVoltageThresholds
      10. 4.2.10 RampTime
      11. 4.2.11 OutOfRegulationWidth
      12. 4.2.12 UnsequenceTime
      13. 4.2.13 EnablePolarity
      14. 4.2.14 SaveRailLog
      15. 4.2.15 ReferenceSelect
      16. 4.2.16 LastUnusedSeq
      17. 4.2.17 IgnoreGlitchAlarms
      18. 4.2.18 IgnoreFlashErrorLog
      19. 4.2.19 Checksum
  7. 5Additional Considerations
    1. 5.1 Embedded Application
    2. 5.2 Timing
      1. 5.2.1 UCD9081 Startup
      2. 5.2.2 Clock Stretching After Flash Erase
      3. 5.2.3 Bit Timeout
      4. 5.2.4 Byte or Transaction Timeout
  8. 6References
  9. 7Revision History

SequenceEventParameters

The SequenceEventParameters field in the configuration parameters specifies the rail identification, monitoring status, and sequencing options for each rail. The address map for these registers is as follows:

AddressSizeDefault ValueDescription
0xE08010x50Rail 1 identification, monitoring status and sequencing options
0xE08110x51Rail 2 identification, monitoring status, and sequencing options
0xE08210x52Rail 3 identification, monitoring status, and sequencing options
0xE08310x53Rail 4 identification, monitoring status, and sequencing options
0xE08410x54Rail 5 identification, monitoring status, and sequencing options
0xE08510x55Rail 6 identification, monitoring status, and sequencing options
0xE08610x56Rail 7 identification, monitoring status, and sequencing options
0xE08710x57Rail 8 identification, monitoring status, and sequencing options
0xE08810x00GPO1 identification, sequencing options
0xE08910x49GPO2 identification, sequencing options
0xE08A10x4AGPO3 identification, sequencing options
0xE08B10x4BGPO4 identification, sequencing options

The format of each register is as follows:

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