SLVAE09B July   2018  – August 2021 TPS560430

 

  1.   Trademarks
  2. 1Introduction
  3. 2Peak Current Mode Loop Modeling
    1. 2.1 Overall Control Block Diagram and Transfer Function Derivation
    2. 2.2 Inside Current Loop Model
    3. 2.3 Overall Loop Model
    4. 2.4 Inductor and Output Capacitor Design Limits
    5. 2.5 The Equation to Calculate Bandwidth and Phase Margin
  4. 3Inductor and Output Capacitor Design
    1. 3.1 Inductor Design
    2. 3.2 Output Capacitor Design
    3. 3.3 Simulation and Bench Verification
  5. 4Summary
  6. 5References
  7. 6Revision History

Overall Loop Model

fZ_EA and fP_EA are zeros and poles introduced by the error amplifier with certain compensation. fZ_OUT and fP_OUT are zeros and poles introduced by the output capacitor and load. fP_ci is the pole introduced by the inside current loop. Based on Equation 1, Equation 6, Equation 7, and Equation 9, the open loop transfer function L(s) around crossover frequency is obtained:

Equation 11. GUID-6F28DD2B-77C7-432B-B262-6088D1B0F348-low.gif

where

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