SLVAE87A December   2020  – October 2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP/BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Re-Clocking
      1. 9.3.1 Design Summary
  13. 10Multi-Drop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Revision History

1 NPN LDO Supply

The device is powered by BAT pin and the LDOIN pin, with which the LDOIN pin is regulated by the pre- regulation circuit form with an external NPN. The device can be powered by a battery module with as low as 9V (without OTP programming) on the BAT pin.

The BAT and LDOIN pins should be filtered separately from the cell. This is to protect against hotplug, in-rush current, and other relevant noise. Recommended filters are RBAT = 30 Ω / .25 W, CBAT = 0.01 µF / 100 V for the BAT pin, two resistors in series for best thermal performance: RNPNC1 = 100 Ω / .75W, RNPNC2 = 200 Ω / .75 W and capacitor CNPNC = 0.22 µF / 100 V for the collector. LDOIN is the input for the external LDO supply for the BQ79616-Q1. Figure 1-1 shows the typical circuit.

GUID-01F832B1-BE6C-4D57-AAEF-BB9A670D6B3C-low.gifFigure 1-1 Power Supply Schematic

The resistor values and NPN can be further optimized from the reference schematic values based on the min and max module voltages for different projects.

Select the NPN Transistor based on the following criteria:

  1. Collector-Emitter Breakdown Voltage (BVCEO) > 80- 100 V (or the module voltage, plus any derating)
  2. DC gain (β, or approximately equal to hfe (AC gain)) > 80 at the expected load current
  3. Collector-based capacitance < 35 pF at typical base-voltage range
  4. Power handling ≥ 1 W
  5. Current handling > 100 mA

The resistor RNPNB in Figure 1-1 serves several purposes:

  1. Limits inrush current
  2. Shares some power dissipation away from the NPN transistor
  3. Combine with the CNPN to serve as a filter
Equation 1. RMAX=VBATmin - VLDOOIN(max) + VCESAT ILOAD(max)

where

  • VBAT(min) is minimum battery module voltage which depends on the number of cells in series and minimum voltage per cell
  • VCE(SAT) = VCE min at VBE(on), from transistor data sheet
  • ILOAD is inrush current during startup or maximum active current and any external loading on CVDD

Connect the filter on the LDOIN supply (CLDOIN ) for stability. Use CLDOIN = 0.1 µF with a voltage rating of 10 V.