SLVAE87A December   2020  – October 2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP/BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Re-Clocking
      1. 9.3.1 Design Summary
  13. 10Multi-Drop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Revision History

5.3 Bus Bar on Individual VC Channel

With the bus bar connected to a VC channel individually, the upper CB pin on that channel shall be left floating to avoid forward biasing the internal CBFET (see Figure 5-5 connection). This connection applies to the bus bar connecting to any middle VC channel individually. That is, in a single device, there is a cell connected above and below the VC channel with the bus bar connected.

To ensure hotplug performance, the CB channel where the bus bar is connected shall still have the differential capacitor CCB in Figure 5-5 , even if the upper CB pin is floating. This capacitor forms a complete capacitor ladder from all the cells and the bus bar connected to the device, allowing high voltage spikes during hotplug to be distributed across the capacitor ladder.

GUID-FE00E91B-7192-4653-9ED7-43DB7D58EEC6-low.jpg
Note: New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in figure, see data sheet for details.
Figure 5-5 Bus Bar Connected any Middle Individual VC Channel

If the bus bar is connected to above the top of a module to an individual VC channel (see Figure 5-6 connection), the upper CB pin on that channel shall left floating, but the CB differential capacitor (CCB in Figure 5-6) shall still be connected. Additionally, an RC filter shall be connected from the top CB pin to the BAT pin. This additional RC filter (using the same RC values as the other RC filters on the CB pins) is to ensure a complete capacitor ladder. It is used to distribute high voltage spikes with the same RC constant as the rest of the CB pins during a hotplug event.

GUID-26AD6D6B-9393-46AE-9BB3-5A0693272E56-low.jpg
Note: New recommendation to add 470 nF/16 V from CB16 to BAT for hotplug robustness not shown in figure, see data sheet for details.
Figure 5-6 Bus Bar Connected Individual VC Channel Above the Top of a Module