SLVAE87A December   2020  – October 2023 BQ79600-Q1 , BQ79612-Q1 , BQ79614-Q1 , BQ79616-Q1 , BQ79652-Q1 , BQ79654-Q1 , BQ79656-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 NPN LDO Supply
  5. 2 AVDD, CVDD outputs and DVDD, NEG5, REFHP and REFHM
    1. 2.1 Base Device
    2. 2.2 Design Summary
  6. 3 OTP Programming
  7. 4 Cell Voltage Sense (VCn) and Cell Balancing (CBn)
    1. 4.1 Cell Voltage Sense (VCn)
    2. 4.2 Cell Balancing (CBn)
      1. 4.2.1 Non-Adjacent Cell Balancing
      2. 4.2.2 Adjacent Cell Balancing
      3. 4.2.3 Cell Balancing With External FET
    3. 4.3 Using Fewer Than 16 Cells
      1. 4.3.1 Design Summary
  8. 5 Bus Bar Support
    1. 5.1 Bus Bar on BBP/BBN
    2. 5.2 Typical Connection
      1. 5.2.1 Cell Balancing Handling
    3. 5.3 Bus Bar on Individual VC Channel
    4. 5.4 Multiple Bus Bar Connections
      1. 5.4.1 Two Bus Bar Connections to One Device
      2. 5.4.2 Three Bus Bar Connections to One Device
      3. 5.4.3 Cell Balancing Handling
  9. 6 TSREF
  10. 7 General Purpose Input-Output (GPIO) Configurations
    1. 7.1 Ratiometric Temperature Measurement
    2. 7.2 SPI Mode
      1. 7.2.1 Support 8 NTC Thermistors With SPI Slave Device
      2. 7.2.2 Design Summary
  11. 8 Base and Bridge Device Configuration
    1. 8.1 Power Mode Pings and Tones
      1. 8.1.1 Power Mode Pings
      2. 8.1.2 Power Mode Tones
      3. 8.1.3 Ping and Tone Propagation
    2. 8.2 UART Physical Layer
      1. 8.2.1 Design Considerations
  12. 9 Daisy-Chain Stack Configuration
    1. 9.1 Communication Line Isolation
      1. 9.1.1 Capacitor Only Isolation
      2. 9.1.2 Capacitor and Choke Isolation
      3. 9.1.3 Transformer Isolation
      4. 9.1.4 Design Summary
    2. 9.2 Ring Communication
    3. 9.3 Re-Clocking
      1. 9.3.1 Design Summary
  13. 10Multi-Drop Configuration
  14. 11Main ADC Digital LPF
  15. 12AUX Anti Aliasing Filter (AAF)
  16. 13Layout Guidelines
    1. 13.1 Ground Planes
    2. 13.2 Bypass Capacitors for Power Supplies and References
    3. 13.3 Cell Voltage Sensing
    4. 13.4 Daisy Chain Communication
  17. 14BCI Performance
  18. 15Common and Differential Mode Noise
    1. 15.1 Design Consideration
  19. 16Revision History

9.2 Ring Communication

The daisy chain communication for the device allows for the use of a ring architecture. In this architecture, a cable break between two devices does not prevent communication to all upstream devices as in a normal non-ring scheme. When the host detects a broken communication interface, the device allows the host to switch the communication direction to communicate with devices on both sides of the break. This allows for safe operation until the break in the lines is repaired.

The CONTROL1[DIR_SEL] controls the communication direction. The devices will reconfigure the COMH and COML ports depends on the [DIR_SEL] and the [TOP_STACK] setting. The auto addressing procedure is needed to re-address the device addresses for the reverse communication direction.

Following is an example on how to change the communication direction to [DIR_SEL] = 1 to the entire daisy chain.

  1. Host clears the previous Top of Stack device
    • In this step, the previous TOS device will re-enable its COMH.
  2. Host sends single device write to change the base device [DIR_SEL] = 1 (see figure (a) in Figure 9-7)
    • The base device will disable its COMH and enable its COML
  3. Host sends broadcast write reverse direction to change the rest of the devices’ [DIR_SEL] = 1 (see figure (b) in Figure 9-7)
    • In this step, the entire daisy chain is set up to communicate in the [DIR_SEL] = 1 direction (i.e. each device set up to transmit command frames sent by host from its COMH to its COML)
  4. Host performs auto addressing procedure to set up device address in the DIR1_ADDR register (see figure (c) in Figure 9-7)
    • Unless the devices have been reset, host can skip the dummy read/write steps to synchronize the DLL in the auto addressing procedure
  5. Host sets up the new Top of Stack device (see figure (c) in Figure 9-7)
    • In this step, the new ToS device disables the COML transmitter
GUID-0C8AA53B-F5A0-42B5-A7CA-2EBEBFA2F1DD-low.jpg Figure 9-7 Example of Changing Communication Direction in Daisy Chain

Ring architecture also enables fault status transmitting in sleep. In SLEEP mode, the following fault detections are still active.

  • Customer and Factory OTP shadowed registers CRC check
  • Device thermal warning
  • Power supplies OV, UV, oscillation detection
  • If OVUV protectors are enabled, cell OV and UV detection
  • If OTUT protectors are enabled, thermistors OT and UT detection

Since communication is not available in SLEEP, the device provides an option to transmit the fault status through Heartbeat (device in no fault state) and Fault Tone (device in fault state). These tones are transmitted in the same direction as a communication command frame, which is based on the CONTROL1[DIR_SEL] setting. In order for the tone signal to return back to the base device (so NFAULT can be triggered if needed), a ring architecture must be used in order to support transmitting the fault status in SLEEP mode.

GUID-7CC12ECE-95C6-46BD-91C1-C199F2A0E935-low.jpg Figure 9-8 Heartbeat or Fault Tone Traveling Direction