SLVAE96A March   2019  – December 2019 TPS6521815 , TPS65218D0

 

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TI Tech Note

Can you change PMICs?

Using a multi-rail power management IC (PMIC) for an applications processor is common, but typically the vendor recommends the PMIC that should be used for each processor. Even if the suggested PMIC is not ideal for the needs of the processor, often the complexity makes it difficult to swap out the PMIC for another solution. The purpose of this tech note is to show that the TPS6521815 PMIC can provide power for the i.MX 7Solo and 7Dual processors.

Why the TPS6521815?

The TPS6521815 device has an input range from 2.7 to 5.5 V, making it appropriate for system-on-module applications powered from a 3.3-V or 5-V DC supply or a Li-Ion battery. The device has four step-down converters that provide the 1-V/1.1-V power rail required for the ARM® and SoC cores, the 1.2-V (or 1.5-V, 1.35-V) rail required for DDR3L (or DDR3, LPDDR3) memory, a 1.8-V rail required for the analog domain plus additional I/Os, and a 3.3-V rail required for VDD_SNVS and I/Os. A low-dropout (LDO) regulator provides 1.5-V for a peripheral IC (mPCIe in this design). Two load switches provide power for USB devices and other peripheral ICs. The TPS6521815 automatically sequences these rails in the correct power-up sequence for the i.MX 7Solo and 7Dual processors.

How do you make the switch?

The TPS6521815 output voltages and sequencing order are determined by an EEPROM-backed register map, which can be programmed using the BOOSTXL-TPS65218 socketed booster pack. Samples of the TPS6521815RSLR can be programmed during the prototype phase of product development and soldered down on the TPS65218EVM-100 or the prototype PCB of the final product to evaluate the performance of the PMIC. To order pre-programmed samples of the TPS6521815RSLR for the NXP i.MX 7Solo, 7Dual processor that match this tech note, contact the programming services organization at ARROW.

Table 1. i.MX 7Solo and 7Dual Power Requirements

TPS6521815 i.MX 7Solo, 7Dual
POWER-UP SEQUENCE POWER SUPPLY (OUTPUT) OUTPUT CURRENT [mA] OUTPUT VOLTAGE [V] POWER SUPPLY (INPUT) VOLTAGE RATING [V] MAX CURRENT [mA]
1 DCDC1 1800 1.0 / 1.1 VDD_ARM, VDD_SOC 0.95 (min), 1.25 (max) 1500
2 DCDC2 1800 1.35(2) NVCC_DRAM, NVCC_DRAM_CKE 1.283 (min), 1.45 (max) 1000
2 DCDC3 1800 1.8 VDDA_1P8_IN, VDD_XTAL_1P8, VDD_LPSR_IN, VDD_TEMPSENSOR_1P8, VDDA_ADCx_1P8, FUSE_FSOURCE, NVCC_SPI, NVCC_SD1-3 1.8 V ± 5% ≈625 + peripheral ICs
2 DCDC4 1600 3.3 NVCC_I2C, NVCC_UART, NVCC_GPIO1-2, NVCC_SD1, NVCC_ENET1, NVCC_SAI, NVCC_LCD, NVCC_EPDC1-2, VDD_USB_OTGx_3P3_IN 3.3 V ± 9.09% ≈150 + peripheral ICs
2 LDO1 400 1.5 Peripheral IC (mPCIe) 250
0 VDD_SNVS_IN(1) 2.4 (min), 3.6 (max) 1
N/A LS2/LS3 1820 5 5-V peripheral ICs >1000
VDD_SNVS_IN supplied directly by coin cell battery in design, but this rail can also be powered DCDC4 in always-on applications without RTC. When VDD_SNVS is powered by DCDC4, this rail must turn on first in the power sequence.
i.MX 7Solo/Dual also support DDR3 (1.5 V) and LPDDR3 (1.2 V) which would require re-programming DCDC2 to output a different voltage.