SLVAEJ5C February 2020 – December 2020 TPS62810-Q1 , TPS62811-Q1 , TPS62812-Q1 , TPS62813-Q1
This document contains information for TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1 (VQFN package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
TPS6281x-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides Functional Safety Failure In Time (FIT) rates for TPS6281x-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total Component FIT Rate | 9 |
Die FIT Rate | 5 |
Package FIT Rate | 4 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS, BICMOSDigital, analog / mixed | 25 FIT | 55 °C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for TPS6281x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
SW no output | 35% |
SW output not in specification – voltage or timing | 45% |
SW power HS or LS FET stuck on | 10% |
PG false trip or fails to trip | 5% |
Short circuit any two pins | 5% |
This section provides a Failure Mode Analysis (FMA) for the pins of the TPS6281x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS6281x-Q1 datasheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
MODE/SYNC | 1 | Intended functionality. | D |
VIN | 2 | Device does not power up. | B |
SW | 3 | Potential device damage. | A |
GND | 4 | No effect. | D |
FB | 5 | Output voltage regulated to VIN (100% mode). | B |
SS/TR | 6 | Device not functional. | B |
COMP/FSET | 7 | Intended functionality. | D |
EN | 8 | Intended functionality. | D |
PG | 9 | Intended functionality. | D |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
MODE/SYNC | 1 | Undetermined device operation. | B |
VIN | 2 | Device does not power up. | B |
SW | 3 | Device not functional, open loop operation. | B |
GND | 4 | Device not functional. | B |
FB | 5 | Undetermined output voltage behavior; open loop operation. | B |
SS/TR | 6 | Intended functionality. | D |
COMP/FSET | 7 | Intended functionality. | D |
EN | 8 | Undetermined device operation; device might power up or not. | B |
PG | 9 | Intended functionality. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
MODE/SYNC | 1 | PG | Device runs FPWM mode once PG is high impedance. | B |
FB | 5 | SS/TR | Undetermined device operation, VOUT spikes up to VIN | B |
SS/TR | 6 | COMP/FSET | Undetermined device operation. | B |
EN | 8 | PG | Device does not power up. | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
MODE/SYNC | 1 | Intended functionality: Forced PWM. | D |
VIN | 2 | Intended functionality. | D |
SW | 3 | Potential device damage. | A |
GND | 4 | Device does not power up. | B |
FB | 5 | Potential device damage. | A |
SS/TR | 6 | Intended functionality. | D |
COMP/FSET | 7 | Intended functionality. | D |
EN | 8 | Intended functionality. | D |
PG | 9 | Potential device damage. | A |