SLVAEL1A November   2020  – January 2021 TPS7B82-Q1

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 DGN Package
    2. 4.2 DRV Package
    3. 4.3 KVU Package

1 Overview

This document contains information for TPS7B82-Q1 (DGN, DRV, and KVU packages) to aid in a functional safety system design. Information provided are:

  • Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
  • Component failure modes and their distribution (FMD) based on the primary function of the device
  • Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

GUID-5F6961F6-F687-4AF4-AAF0-D7A9DD0CB667-low.gif Figure 1-1 Functional Block Diagram

TPS7B82-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.