SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

D Example With I2C Serial Interface

The TPS6594-Q1 example in Table 11-1 is taken from the Scalable PMIC GUI implementation. In this example, the initial I2C address of the target device is 0x48 and the updated I2C address is 0x28.

Table D-1 I2C Example With Updated I2C1 Address
Instruction I2C Address (Page) Read/Write Register Address Data Description
1 0x48 (0) Write 0xA2 0x00 Reset unlock logic
2 0x48 (0) Write 0xA2 0x98 NVM unlock
3 0x48 (0) Write 0xA2 0xB8
4 0x48 (0) Write 0xA2 0x13
5 0x48 (0) Write 0xA2 0x7D
6 0x48 (0) Read 0xA3 0xC0 Confirm that the NVM was successfully unlocked; bit 6 is set.
7 0x48 (0) Write 0xA3 0xC1 Halt the PFSM
8 0x49 (1) Write 0x18 0x0D This instruction unlocks the frequency selection so that the BUCK frequency (register 0x8A of page 0) can be changed along with other updates to page 0. This register is set to the appropriate application value when page 1 is updated.
9 0x48 (0) Write 0x31 0x20 Update GPIO1, GPIO2, and GPIO3 (LP876x) to the desired final serial interface settings.
10 0x48 (0) Write 0x32 0x40
11 0x48 (0) Write 0x33 0x10
12 0x49 (1) Write 0x22 0x28 Update I2C1 address to 0x28. All of the following register accesses are based upon this address.
13 0x29 (1) Write 0x23 0x12 Update the I2C2 address to 0x12
14 0x29 (1) Write 0x1A 0x00 Update the Serial Interface mode. At this point if the serial interface was changed to SPI or the CRC enabled, then the associated changes must be made before proceeding to the next instruction.
15 0x28 (0) Write 0x04-0xD1 Array Write content to page 0 register map based upon Table 8-1. Return registers found in Table 9-1 to default values.
16 0x29 (1) Write 0x01-0x43 Array Write content to page 1 register map based upon Table 8-1
17 0x12 (4) Write 0x05,0x09 Array Write contents to page 4
18 0x28 (0) Write 0xA4 0x00 Set PFSM control to sub-page 0
19 0x2B (3) Write 0x00-0xFF Array Write content to page 3 sub-page 0
20 0x28 (0) Write 0xA4 0x01 Set PFSM control to sub-page 1
21 0x2B (3) Write 0x00-0xFF Array Write content to page 3 sub-page 1
22 0x28 (0) Write 0xA4 0x02 Set PFSM control to sub-page 2
23 0x2B (3) Write 0x00-0xFF Array Write content to page 3 sub-page 2
24 0x28 (0) Write 0xA4 0x00 Set PFSM control to sub-page 0
25 0x28 (0) Write 0xF0-0xFB 0x00 Clear register CRC content
26 0x28 (0) Write 0xEF 0x02 Run CRC BIST and update the register CRC values
27 0x28 (0) Read 0xFB Non-zero value This is a simple check to see if the crc is complete. The check is simply looking to see if the value was updated from 0x00 (cleared in step 24).
28 0x28(0) Write 0xF0-0xF3 Array Compute the 16-bit User register CRC values and update the REGMAP_USER_INCLUDE_PERSIST_CRC16 and REGMAP_USER_INCLUDE_EXCLUDE_CRC16 registers.
29 0x29 (1) Write 0xE1 0x00 Prepare NVM to receive update from register map. If the desire is to lock the EEPROM so that future updates cannot be made, then before the transfer command, write any value other than 0xA5 to address 0x141: Page 1 register address 0x41.
30 0x29 (1) Write 0xEF 0x02 Start the transfer from the register map to the NVM.
31 0x29 (1) Read 0xF3 0x04 Poll bit 1. When bit 1 is cleared, the transfer is complete. Bit 2 can be either '0' or '1'.
32 0x28 (0) Write 0xA2 0x00 Reset unlock logic