SLVAF93A october   2022  – april 2023 LP8764-Q1 , TPS6594-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Hardware and PMIC Setup
  5. 3Configuration Overview
  6. 4Instructions
  7. 5Special Considerations
    1. 5.1 Changing the Serial Control Interface
    2. 5.2 Updating the Frequency Selection
    3. 5.3 PFSM
    4. 5.4 Permanently Locking the NVM
    5. 5.5 Updating the Register CRC
  8. 6NVM Validation
  9. 7References
  10.   A Registers Backed by NVM
  11.   B Non-NVM Registers Which are Part of the Register CRC
  12.   C CRC for User Registers, Page 0 and Page 4
  13.   D Example With I2C Serial Interface
  14.   E Revision History

2 Hardware and PMIC Setup

The hardware connections are described in the schematic checklist (see Reference 6). Table 2-1 and Table 2-2 show the required connections associated with NVM configuration.

Table 2-1 Subset of Schematic Checklist for TPS6594-Q1 and TPS6593-Q1
Pin Name Purpose Connection for Functional Use
2 VOUT_LDOVINT Output pins of internal LDOs for noise decoupling capacitor Capacitor: Ctyp = 2.2 µF;
Vcap > 6.3 V
3 VOUT_LDOVRTC
4 VCCA Analog input voltage for the internal LDOs and other internal blocks Capacitor: Cmin = 0.47 µF;
Ctyp = 1 µF; Vcap>6.3 V
5 REFGND1 System reference ground Connect to solid ground plane but not the thermal pad on the top layer.
6 REFGND2
30 SDA_I2C1, SDI_SPI I2C or SPI data Connect to data line of controller. For I2C use resistor value depending upon speed and PCB.
31 SCL_I2C1/SCK_SPI I2C or SPI clock Connect to clock line of controller. For I2C use resistor value depending upon speed and PCB.
32 CS_SPI1 SPI Chip select Connect to CS of SPI controller
33 SDO_SPI1 SPI SDO Connect to SDO of SPI controller
48 VIO_IN Digital supply input for GPIOs and I/O supply voltage Capacitor: Cmin = 0.47 µF;
Ctyp = 1 µF; Vcap > 6.3 V
57 Thermal Pad Power ground, which is also the thermal pad of the package. Connect to top layer power ground polygon
(1) Pins 32 and 33 are only needed for SPI communication. With I2C only pins 30 and 31 are needed.
Note: Refer to the schematic checklist for the latest HW guidance.

Table 2-2 Subset of Schematic Checklist for LP8764-Q1
Pin Name Purpose Connection for functional use
20 VOUT_LDO Output pin of internal LDO for noise decoupling capacitor Capacitor: Ctyp = 2.2 µF;
Vcap > 6.3 V
18 VCCA Analog input voltage for the internal LDOs and other internal blocks Capacitor: Cmin = 0.1 µF;
Ctyp = 0.47 µF; Vcap > 6.3 V
19 AGND1 System reference ground Connect to solid ground plane but not the thermal pad on the top layer.
21 AGND2
5 SDA_I2C1, SDI_SPI I2C or SPI data Connect to data line of controller. For I2C use resistor value depending upon speed and PCB.
4 SCL_I2C1/SCK_SPI I2C or SPI clock Connect to clock line of controller. For I2C use resistor value depending upon speed and PCB.
2 CS_SPI(1) SPI Chip select Connect to CS of SPI controller
3 SDO_SPI(1) SPI SDO Connect to SDO of SPI controller
24 VIO Digital supply input for GPIOs and I/O supply voltage Capacitor: Cmin = 0.1µF;
Ctyp = 0.47 µF; Vcap > 6.3 V
13/29 PGND Power Ground Connect to top layer power ground polygon
(1) Pins 2 and 3 are only needed for SPI communication. With I2C only pins 4 and 5 are needed.

VCCA and VIO must be applied and the serial interface must be accessible to update the NVM. The VIO must not be connected to or dependent upon any GPIO or regulator from the PMIC. Similarly, in the case of an I2C serial interface, the pullup voltage must also be independent of the PMIC. When configuring the NVM via I2C only the I2C1 interface is needed. The I2C2 interface is only used in the application when enabled and utilized solely for the watchdog communication.

The initial PMIC state must also be understood before attempting to configure the NVM. Generally, the PMIC must be in a static or idle state. In some NVM configurations, the PMIC does not power up until the ENABLE pin is activated. Simply holding the ENABLE pin low can be an effective means to hold the PMIC in a known static state.

Also, if the NVM is configured to loop continuously between states polling for a certain condition, this can interfere with the initial steps in the configuration which unlocks the NVM.

Finally, the PMIC does allow for the NVM to be configured while in the safe recovery hardware state. This provides a means to change the NVM in the event that the NVM was erroneously configured and results in an error or shutdown. When defining an NVM, a transition to the safe recovery state is important and must not be omitted. Examples which include the transition to safe recovery are provided in the Scalable PMIC GUI as templates. If a transition is not provided, then the associated interrupts must be serviced for the NVM to be unlocked successfully.