SLVAFG5 November   2022 TPS929240-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Device Overview
    2. 1.2 BCI Test Method
  4. 2PCB Design Recommendation
    1. 2.1 Schematic Design
    2. 2.2 Layout Design
  5. 3BCI Test
    1. 3.1 Test Set-up
    2. 3.2 Test Results
  6. 4Summary
  7. 5References

2.1 Schematic Design

Figure 2-1 is the schematic of TPS929240-Q1 EVM.

  • Placing a 4.7 μF (C9) and a 100 nF (C16) decoupling ceramic capacitors close to the VBAT pin of each TPS929240-Q1 is highly recommended to obtain good EMC performance.
  • Adding the same value capacitors is also required for SUPPLY input (C10 and C17) and VLDO output (C11 and C18).
    • C10 and C17 can be added after anti-reverse diode D57. D57 acts as a filter to pass positive noise and block negative noise so that the common-mode noise entering the control module decreases.
  • Placing a typically 1 nF ceramic capacitor (C20) in parallel with RREF close to the VREF pin to improve the noise immunity.
    • The capacitance of C20 can up to 2.2 nF.
  • To achieve good EMC performance, TI recommends adding a 1 nF ceramic capacitor (C30-C53) on each of the output channels.
  • TPS929240-Q1 EVM jumpers configuration during test:
    • On board buck is used to output 5.5V for SUPPLY.
    • RREF is set to 6.34kΩ.
Figure 2-1 TPS929240-Q1 Schematic for PCB Design