SLVAFJ3 september   2023 LM5177 , LM51772

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Importance of DC-DC Power Supply Layout
  5. 2Steps for a Good Layout
    1. 2.1 Identifying Critical Circuit Paths
    2. 2.2 Optimizing Hot Loops in the Power Stage
    3. 2.3 Separating Differential Sense Lines From Power Planes
      1. 2.3.1 Using Net Ties to Separate Routing
    4. 2.4 Routing Gate-Drive and Return Paths
    5. 2.5 Controller Layout
    6. 2.6 Separate AGND and PGND
    7. 2.7 Thermal Vias
  6. 3Tips for Layout Optimization
  7. 4Layout Example
  8. 5Summary
  9. 6References

2.1 Identifying Critical Circuit Paths

A good layout begins by identifying these critical components

  • High di/dt loops or hot loops.
  • High dv/dt nodes.
  • Sensitive traces.
GUID-20230210-SS0I-MZFM-N3PV-R7RVVP8WLPPH-low.svg Figure 2-1 Identifying High di/dt Loops, High dv/dt Nodes and Sensitive Traces

Figure 2-1 shows the high di/dt paths in the converter controller by LM5177 . The most dominant high di/dt loops are the input-switching current loop and output-switching current loop. The input loop consists of an input capacitor (CIN), and MOSFETs (Q1 and Q2). The output loop consists of an output capacitor (COUT), and MOSFETs (Q3 and Q4), along with their return paths.

The high dv/dt nodes are those with fast voltage transitions. These nodes are the switch nodes (SW1 and SW2), the boot nodes (HB1 and HB2), and the gate-drive traces (HO1, LO1, HO2 and LO2). The areas of the switching nodes SW1 and SW2 need to be as small as possible. If the SW1 and SW2 are poured with big area copper planes, the high dv/dt noisy signal can couple into other traces nearby through capacitive coupling, which causes electromagnetic interference issues.

The current-sense traces from resistor RS to the integrated circuit (IC) pins (CSA and CSB), the input or output sense traces (ISNSP, ISNSN, FB), and the control components (SLOPE, RCOMP, CCOMP, CHF) form the noise-sensitive traces.

For good layout performance, optimize the surface areas of high dv/dt nodes, and keep the noise-sensitive traces away from the noisy (high di/dt and high dv/dt) portions of the circuit and minimize thier loop areas.