SLVAFP9 October   2024 TPS65219 , TPS6521905

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2TPS65219 Overview
  6. 3Power Delivery Networks
    1. 3.1 Always ON: Designed for Cost (-1 and -2 Devices)
    2. 3.2 Always On: Designed for Power and or Efficiency (-1L and -2L Devices)
    3. 3.3 Always On: Designed for PL Performance (-3 Devices)
    4. 3.4 Full Power Management Flexibility (All Speed Grade)
  7. 4Loading a NVM Configuration File to PMIC
  8. 5Summary
  9. 6References

3 Power Delivery Networks

The Xilinx UltraScale MPSoCs require multiple power rails to support a variety of features. Some of the power domains can be consolidated to optimize the power design in terms of cost, efficiency or performance. This section describes the Power Delivery Network (PDN) for each of the power supply consolidations. All PDN use TPS65219 (user-programmable) which can be configured and optimized to meet different application needs. In addition to this applications note, TI also provides the PMIC NVM configuration files to assist with the design process. These NVM files have the default register settings that are used on each power delivery network (PDN) and can be easily uploaded into the TPS65219-GUI for re-programming.

Table 3-1 shows the options for power supply consolidation based on the speed grade. The power design on each PDN follows the recommended PL power supply sequencing to help achieve minimum current draw and to make sure the I/Os are 3-stated at power-on.

Table 3-1 Power Supply Consolidation
Power Supply Consolidation Speed Grade Power Delivery Network (PDN)
Always On: Optimized for Cost

-1 and -2 Devices

 Section 3.1
Always On: Optimized for Power/Efficiency -1L and -2L Devices Section 3.2
Always On: Optimized for PL Performance -3 Devices Section 3.3
Full Power Management Flexibility All Speed Grades/Devices Section 3.3